Senior Engineer, Physical Design AI/ML

What you'll do

• Build and implement machine learning and generative models to optimize chip layout designs for PPA efficiency.
• Automate design implementation steps including floor-planning, placement, routing, and clock tree synthesis.
• Automate verification processes such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) checks.
• Develop automated QA systems and tools for exploratory PDK generation.
• Apply machine learning techniques to extract correlations between device data, benchmark circuits, and operating conditions.
• Create internal benchmarking capabilities and assessments to share with the R&D team.
• Research and evaluate new device architectures, materials, and integration schemes for sub-2nm technology nodes.

What we're looking for

• A PhD degree is preferred.
• Experience in RTL synthesis, place and route, and timing analysis is required.
• Proficiency in Python or C++ with expertise in PyTorch and TensorFlow is required.
• Hands-on experience with machine learning for engineering applications like regression, surrogate modeling, and graph neural networks is required.
• Experience using Bayesian optimization or active learning frameworks for design space exploration is required.
• Expertise in agentic AI frameworks such as LangGraph, CrewAI, or ADK is required.
• Proficiency in EDA tools for synthesis and layout is preferred.
• Experience with generative AI for chip design or optimization is preferred.