Senior Engineer, Physical Design AI/ML

What you'll do

• Design and implement machine learning and generative models to optimize chip layout for PPA efficiency.
• Automate design implementation steps including floor-planning, placement, routing, and clock tree synthesis.
• Automate verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) checks.
• Develop and automate exploratory PDK generation and internal QA systems.
• Apply machine learning to extract correlations between device data, benchmark circuits, and operating conditions.
• Develop internal benchmarking capabilities and assessments to share with the R&D team.
• Research and evaluate new device architectures, materials, and integration schemes for sub-2nm technology nodes.

What we're looking for

• Demonstrated skills in applying AI/ML tools to improve design simulation accuracy and throughput for PPA.
• Experience in optimization of design-technology co-optimization (DTCO) knobs in advanced logic nodes (2nm or beyond) (preferred).
• Demonstrated skills in standard cell architecture creation, logic cell library characterizations, Place and Route, and PDK generation.
• Strong understanding of Logic process integration.
• PhD with industry experience (preferred).
• Skills in RTL synthesis, place and route, and timing analysis.
• Understanding of clock and power delivery network schemes.
• Hands-on experience with ML/deep learning projects for scientific or engineering applications, including regression, surrogate modeling, and graph neural networks.
• Strong Python and/or C++ skills with expertise in PyTorch and Tensorflow.
• Experience using Bayesian optimization and/or active learning frameworks for design space exploration.
• Expertise with agentic AI frameworks such as LangGraph, CrewAI, and ADK.
• Proficiency in EDA tools for synthesis and layout (preferred).
• Prior experience using generative AI for chip design or optimization (preferred).