Senior Physical Design Methodology Engineer, PPA Fusion Compiler

Nvidia

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TXHillsboro, OR
Employment: Full-time
Posted: 36 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $204k

$153k most similar roles pay here $276k

This listing doesn't post a salary. Most similar roles pay $177,250–$231,150.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1392 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1041 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Physical Design Methodology Engineer, PPA Fusion Compiler

Role Posting Log in to save

As a Senior Physical Design Methodology Engineer, PPA Fusion Compiler, you will join the Networking Silicon engineering team to develop efficient physical design methodologies for graphics processors and SOCs. You will be responsible for creating unique solutions to state-of-the-art physical design problems to improve power, performance, and area. Your daily work involves developing flow and tool methodologies for place and route, timing analysis and closure, IR/Signal-EM convergence, power and noise analysis, and back-end verification. You will also perform data-based analysis and algorithmic solutions for PPA improvement. The role requires expertise in ML-based solution development, floor planning, clock and power distribution, and thermal management. You must be proficient with standard industry PnR tools and capable of extensive scripting to address design issues like yield, manufacturability, and physical convergence across multiple projects.

Skills

Physical Design P&R Timing Analysis IR/Signal-EM Floor planning Power Distribution Clock Distribution Scripting Verification

What you'll do

Develop efficient physical design methodologies for graphics processors and SOC implementations.
Create unique solutions to solve state-of-the-art physical design problems to improve PPA.
Formulate and develop machine learning-based solutions for physical design challenges.
Develop flow and tool methodologies for Place and Route (P&R) and timing analysis.
Manage convergence in IR, Signal-EM, power, and noise analysis across multiple projects.
Perform data-based analysis and algorithmic solutions for PPA checks and improvements.
Execute extensive scripting to check and improve Power, Performance, and Area metrics.

What we're looking for

MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
10+ years of experience in Physical Design Engineering.
Experience and proven implementation of ML-based solutions for physical design.
Knowledge of chip design aspects including floor planning, clock/power distribution, place and route, integration, and verification.
Expertise in timing, EM, and IR convergence with optimal PPA.
Strong background in hierarchical design approach, top-down design, budgeting, and physical convergence.
Familiarity with process-related issues such as Design for Yield, Manufacturability, and thermal management.
Proficiency with standard industry PnR tools and extensive scripting capabilities to improve PPA.

Save