Senior Physical Design Engineer

Microsoft

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$119,800–$234,700 / yr
Posted
5 days ago
Freshness
Confirmed live yesterday
Closes
Mar 17, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $182k
This role $177k
$106k most similar roles pay here $248k

This role pays more than 59% of similar roles. Most pay $155,000–$209,006 — the shaded band above. At the midpoint, this role pays about $177k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 588 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 570 roles with salary data.

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At a glance

TL;DR · Senior Physical Design Engineer

The Senior Physical Design Engineer joins the Compute Silicon & Manufacturing Engineering team to support the development of advanced computer chips like Azure Cobalt. This role involves driving end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. The engineer is responsible for clock construction, CTS, and RTL to GDS implementation while influencing design tools and methodologies through a data-driven approach. Key responsibilities include collaborating with CAD, RTL, DFT, Architecture, Power & Performance, and Technology teams to optimize SOC blocks. The role requires expertise in advanced foundry process nodes, low power design methodology for SOC, and managing trade-offs across power, performance, and area. Candidates must demonstrate proficiency in floorplanning, extraction, and various clock construction strategies for high speed designs.

What you'll do

  • Execute end-to-end physical design from synthesis through place-and-route for large designs.
  • Complete all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
  • Manage clock construction and Clock Tree Synthesis (CTS) for high-speed designs.
  • Conduct methodology exploration to optimize SOC blocks for clock construction and related processes.
  • Implement RTL to GDS transitions within the Physical Design domain.
  • Influence design tools, flows, and methodologies using a data-driven approach.
  • Partner with CAD and methodology teams to identify and resolve technical flow issues.

What we're looking for

  • A Doctorate in Electrical Engineering, Computer Engineering, or Computer Science with 1+ years of experience, OR a Master's degree with 4+ years, OR a Bachelor's degree with 5+ years.
  • Ability to pass the Microsoft Cloud Background Check and meet government security screening requirements.
  • Must provide proof of citizenship, residency, or other protected status to access export-controlled information.
  • Experience in semiconductor design (preferred).
  • Proven track record in Physical Design including synthesis, floorplanning, place and route, extraction, timing, and physical verification (preferred).
  • Production silicon tape-out experience in advanced foundry process nodes (preferred).
  • Expertise in low power design methodology for SOC and understanding of PPA trade-offs (preferred).
  • Familiarity with clock construction strategies for high speed designs (preferred).

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