Senior Physical Design Engineer

Samsung Semiconductor

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $138,000–$206,000 / yr
Posted: 23 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $182k

This role $172k

$128k most similar roles pay here $228k

This role pays less than 57% of similar roles. Most pay $155,675–$208,200 — the shaded band above. At the midpoint, this role pays about $172k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 49 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

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At a glance

TL;DR · Senior Physical Design Engineer

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Senior Physical Design Engineer joins the AGI Computing Lab to address complex system-level challenges posed by growing demands for AI/ML workloads. This role involves owning the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis, and routing. The engineer will drive PPA convergence, perform static timing analysis, manage power delivery networks, and execute physical verification on advanced FinFET process nodes. Key responsibilities include developing automated flows using Tcl, Python, or Perl scripting and agentic AI tools. Required expertise includes proficiency with Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC. The role focuses on solving hardware-software balance issues for high-bandwidth interconnect subsystems and memory controllers while optimizing performance, power, and area in a high-performance computing environment.

Skills

ASIC SoC RTL GDSII Synthesis Floorplanning Clock Tree Synthesis STA SDC UPF CPF DRC LVS Tcl Python Perl FinFET NoC AI/ML

What you'll do

Own the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII.
Drive block- and full-chip-level PPA convergence and timing closure across multiple process corners.
Develop floorplans, power delivery networks, and macro placement strategies for memory controllers and interconnect subsystems.
Perform static timing analysis (STA), constraint development, and signoff to resolve IR-drop and signal integrity issues.
Execute physical verification and signoff including DRC, LVS, and reliability checks on advanced process nodes.
Provide physical feedback to RTL and verification engineers to inform design-for-PPA and floorplan-aware microarchitecture decisions.
Develop and automate physical implementation flows using Tcl/Python scripting and agentic AI tools.

What we're looking for

Bachelor’s with 5+ years, Master’s with 3+ years, or PhD with 0+ years of experience.
Strong background in digital physical design and VLSI implementation.
5+ years of experience in physical design including synthesis, floorplanning, P&R, CTS, and timing closure for complex ASIC/SoC designs.
Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC.
Experience with static timing analysis (STA), SDC development, low-power design (UPF/CPF), and power/IR-drop/electromigration analysis.
Experience with physical verification (DRC, LVS, antenna) and tapeout on advanced FinFET process nodes.
Experience implementing memory controllers, NoC, or high-speed interconnect IP and full-chip SoC integration.
Proficiency in scripting languages such as Tcl, Python, or Perl for physical design flow automation.

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