below marketmost similar roles pay hereabove market
This role pays less than
71%
of similar roles. Most pay
$169,175–$216,250
— the blue band above.
At the midpoint, this role pays about
$172k
versus about
$193k
for comparable roles.
Based on 240 similar postings.
Employer
About Samsung Semiconductor
Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.
Samsung Semiconductor currently has
36 open roles
on FindRole.
Listed pay typically runs
$163,000–$253,000
across 36 roles with salary data.
The Senior Physical Design Engineer joins the AGI Computing Lab to address complex system-level challenges for future AI/ML workloads. This role involves owning the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII. Key responsibilities include synthesis, floorplanning, placement, clock tree synthesis, and routing to achieve PPA convergence and timing closure. You will develop power delivery networks for memory controllers and high-bandwidth interconnect subsystems while performing static timing analysis and physical verification on advanced FinFET process nodes. The position requires proficiency with Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC, along with Tcl and Python scripting. You will also utilize agentic AI tools to automate flows, ensuring scalable platforms meet demanding computational and memory requirements while minimizing energy consumption.
What does a Physical Design Engineer earn?
Median $177300 from 31 postings across 9 companies.
Own the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII.
Drive block- and full-chip-level PPA convergence and timing closure across multiple process corners.
Develop floorplans, power delivery networks, and macro placement strategies for memory controllers and interconnect subsystems.
Perform static timing analysis, constraint development, and signoff to resolve timing, IR-drop, and signal integrity issues.
Execute physical verification and signoff including DRC, LVS, and reliability checks on advanced process nodes.
Provide physical feedback to RTL and verification engineers to inform design-for-PPA and floorplan-aware microarchitecture decisions.
Develop and automate physical implementation flows using Tcl/Python scripting and agentic AI tools.
What we're looking for
Bachelor’s with 5+ years, Master’s with 3+ years, or PhD with 0+ years of industry experience.
Strong background in digital physical design and VLSI implementation.
5+ years of experience in physical design implementation for complex ASIC/SoC designs, including synthesis, floorplanning, place-and-route, CTS, and timing closure.
Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC.
Experience with static timing analysis, constraint (SDC) development, low-power design (UPF/CPF), and power, IR-drop, and electromigration analysis.
Experience with physical verification (DRC, LVS, antenna) and tapeout on advanced FinFET process nodes.
Experience implementing memory controllers, NoC, or high-speed interconnect IP and full-chip SoC integration.
Proficiency in scripting (Tcl, Python, or Perl) for physical design flow automation.
VLSI Physical Design
RTL2GDS
Place and Route
Timing Closure
Power and Clock Distribution
Physical Verification
IR Drop Analysis
RC Extraction
Synopsys (ICC2
Cadence (Genus
Python
Perl
Tcl
Make
ML
AI