Senior SOC Physical Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $131,175–$173,400 / yr
Posted: 15 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k

This role $152k

$117k most similar roles pay here $264k

This role pays less than 91% of similar roles. Most pay $176,650–$227,500 — the shaded band above. At the midpoint, this role pays about $152k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 564 open roles on FindRole.

Listed pay typically runs $152,130–$222,500 across 550 roles with salary data.

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At a glance

TL;DR · Senior SOC Physical Design Engineer

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As a Senior SOC Physical Design Engineer within the ASICS Engineering group, you will independently manage physical design flows for high-speed DDR, graphics, and micro-architecture. Your daily responsibilities involve floor planning, clock tree synthesis, place and route, power distribution network design, and timing analysis to optimize power utilization and performance for system-on-chip products. You will perform critical physical verification checks including LVS, DRC, design-for-manufacturing, and design-for-yield at both the chip and block levels. The role requires providing schedules and supporting cross-functional engineering efforts to achieve signoff closure for tapeout while contributing to design reviews and project meetings. You will work on complex technical problems involving SOC algorithm design and modeling. Required expertise includes physical verification flows and advanced methodology to ensure high-performance results in the system-on-chip product space.

Skills

Physical Design Floor Planning Clock Tree Synthesis Place and Route PDN Timing Analysis LVS DRC SoC DDR Micro-architecture

What you'll do

Execute physical design flows for high-speed DDR and graphics components.
Perform floor planning, clock tree synthesis, and place and route tasks.
Conduct power distribution network (PDN) analysis and optimization.
Perform timing analysis and ensure closure for SoC products.
Execute physical verification checks including LVS, DRC, DFM, and D1Y.
Develop micro-architecture designs, SOC algorithms, and modeling methodologies.
Manage project schedules and cross-functional efforts to achieve tapeout signoff.

What we're looking for

A Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is accepted.
Experience in Physical Design Flow for high-speed DDR and graphics.
Expertise in physical verification flows, micro-architecture, SoC algorithm design, and modeling.
Proficiency in Floor Planning, Clock Tree Synthesis, Place and Route, and PDN.
Ability to perform timing analysis and closure.
Experience performing physical verification checks such as LVS, DRC, and design-for-manufacturing/yield at chip and block levels.

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