Browse tech roles

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification +9 more Show less

ASIC Design RTL Design Logic Synthesis Timing Analysis SoC Integration Python Perl C++ UCIe Digital Design Verification Methodology Boot Controllers Reset Controllers Memory Controllers DMA +10 more Show less

System Verilog UVM Python Verilog RTL VCS Verdi OOPS ASIC Verification Computer Architecture Functional Coverage Scripting +7 more Show less

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation +12 more Show less

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT RTL Noise Analysis Placement Routing Equivalence Checking Scan BIST AMS GPU LPU +10 more Show less

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic +11 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

ASIC Design RTL Design Verilog System Verilog Python Perl Logic Synthesis Timing Analysis VLSI Computer Architecture VCS Verdi GDB Functional Coverage Assertion-Based Verification Embedded Processors SoC GPU +13 more Show less

System Verilog UVM VCS Verdi Indago GDB C/C++ Perl Assertion-Based Verification Functional Coverage Random Stimulus ASIC Verification Post-silicon Verification +8 more Show less

System Verilog UVM Python TCL Perl Verdi DVE JTAG MBIST DFT Scan Architecture Boundary Scan ATE post silicon validation +9 more Show less

Physical Design Python C++ Perl DFT Place and Route Timing Closure Power/Clock/Reset Distribution Agentic AI Chiplet Packaging Algorithm Development +7 more Show less

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces +10 more Show less

DFT MBIST ATE Verilog Python TCL Perl DVE Verdi SRAM DRAM Synopsys DesignWare SMS TestMax Mentor Graphics Tessent +10 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV SOC Verification +6 more Show less

ASIC Design RTL Verilog Micro-architecture VLSI Logic Synthesis Timing Analysis DFT Computer Architecture PCI-Express CXL Python Perl C/C++ CMOS Post-silicon Validation Floor-planning ECO Bus Protocols Interconnect Networks +15 more Show less

System Verilog UVM C++ Python Perl ASIC Verification Formal Verification Constraint Random Verification Logic Design Coverage Metrics DFT IST Object-Oriented Programming X prop +9 more Show less

SystemVerilog UVM C++ VCS Digital Design Computer Architecture Assertion-Based Verification Functional Coverage Random Stimulus GDB Debussy Object-Oriented Programming Processor Pipeline Verification ASIC Verification +9 more Show less

ASIC Post-Silicon Validation Python C System Verilog UVM PCIe Ethernet I2C SPI JTAG Firmware Bootloaders DFT ATE Oscilloscopes Traffic Generators HBM DDR +14 more Show less