Senior ASIC Engineer, Post Silicon Validation

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Nov 30, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $206k
$139k most similar roles pay here $257k

This role pays more than 56% of similar roles. Most pay $168,200–$217,500 — the shaded band above. At the midpoint, this role pays about $206k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 202 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 156 roles with salary data.

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At a glance

TL;DR · Senior ASIC Engineer, Post Silicon Validation

Senior ASIC Engineer - Post Silicon Validation joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. This role involves planning and setting up silicon bring-up infrastructure, including system boot, initialization, and power-on of ASICs. The engineer will collaborate with design, verification, and board teams to root-cause functional and electrical issues while executing test plans for IP, subsystem, and full-chip stress testing. Key responsibilities include developing automation frameworks, performing characterization using oscilloscopes and traffic generators, and providing feedback on yield issues and silicon errata. Required skills include experience with I2C, SPI, JTAG, PCIe, and Ethernet protocols, alongside proficiency in C, Python, and scripting for validation automation. The role addresses the critical transition from pre-silicon verification to post-silicon validation within the high-performance networking and infrastructure domain.

What you'll do

  • Plan and set up silicon bring-up infrastructure including system boot, initialization, and power-on for ASICs.
  • Root-cause and resolve functional and electrical issues in coordination with design, verification, and board teams.
  • Develop and execute validation test plans for IP, subsystem, and full-chip stress testing and corner case analysis.
  • Build and extend post-silicon validation infrastructure, automation tools, and result analysis frameworks.
  • Utilize lab instrumentation such as oscilloscopes, analyzers, and traffic generators for validation and characterization.
  • Provide feedback on test escapes and yield issues to influence silicon revisions and firmware workarounds.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering with 7+ years experience, Master's with 4+ years, or PhD with 1+ year.
  • Experience in post-silicon validation, bring-up, and debug with ASICs.
  • Experience in early silicon bring-up, debug, and validation.
  • Experience bringing up standard peripheral interfaces (I2C, SPI, JTAG) and protocols (PCIe, Ethernet).
  • Experience working with firmware, bootloaders, and low-level silicon debug environments.
  • Fluency in C, Python, and scripting for validation automation.
  • Experience with memory subsystems (HBM, DDR) (preferred).
  • Experience with electrical/thermal performance characterization or System Verilog/UVM/emulation-based verification (preferred).

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