Senior ASIC Verification Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TXORWACA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 22 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$125k $236k

below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $168,500–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Verification Engineer

Role Posting Log in to save

The Senior ASIC Verification Engineer joins the NVIDIA Clocks Team to deliver high-quality clocking and reset logic for SOC and GPU ASIC products. This role involves owning the end-to-end validation of clocking structures in Tegra and GPU products, including test plan development, automation, validation flows, coverage metrics, and bug identification. The engineer must develop scalable solutions to address complex design specifications while balancing infrastructure constraints and multi-platform support. Key responsibilities include partnering with architecture teams and coordinating across time zones. Required technical skills include expertise in SystemVerilog, UVM, C++, Perl, and Python, alongside knowledge of constraint random verification, Formal Verification, and profiling tools. The work focuses on solving sophisticated clocking and reset design problems for data centers, consumer graphics, self-driving cars, and artificial intelligence.

Skills

System Verilog UVM C++ Python Perl ASIC Verification Formal Verification Constraint Random Verification Logic Design Coverage Metrics DFT IST Object-Oriented Programming X prop

What you'll do

Own the end-to-end validation of clocking structures for Tegra and GPU products.
Develop comprehensive test plans, automation flows, and coverage metrics for clocking designs.
Execute tests to identify, track, and fix bugs within the clocking and reset logic.
Code verification environments using SystemVerilog, UVM, C++, Perl, and Python.
Develop scalable verification solutions that work across multiple platforms and products.
Partner with architecture and design teams to validate complex clocking specifications.
Automate tasks within the design verification process to improve testing speed and re-usability.

What we're looking for

BS or MS in EE/ECE or equivalent experience.
5+ years of relevant industry work experience.
Good understanding of Logic Design and Architecture.
Expertise in SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, and X prop.
Strong coding skills in System Verilog, C++, and scripting languages like Perl and Python.
Prior experience in implementing Test plans for pre-silicon platforms.
Experience automating tasks in the design verification process (preferred).
Hands-on experience in object-oriented programming (preferred).

Save