Senior ASIC Verification Engineer

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $136,000–$218,500 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$126k most similar roles pay here $230k

This role pays less than 53% of similar roles. Most pay $168,500–$216,062 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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The Senior ASIC Verification Engineer joins the Clocks Team to deliver high-quality clocking and reset logic for various units in SOC and GPU ASIC products. This role involves owning the validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, coverage metrics, and bug identification. The engineer will tackle sophisticated problems by developing scalable solutions across platforms while partnering with architecture and design teams. Required skills include expertise in System Verilog, UVM, C++, Perl, and Python, alongside experience with constraint random verification, Formal Verification, and profiling tools. The work focuses on solving complex clocking and reset design challenges to ensure bug-free designs for products spanning data centers, consumer graphics, self-driving cars, and artificial intelligence. The role requires a deep understanding of logic design and architecture.

Skills

System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Coverage Metrics Logic Design ASIC Verification DFT IST Object-Oriented Programming Automation

What you'll do

Own the end-to-end validation of clocking structures for Tegra and GPU products.
Develop comprehensive test plans, automation scripts, and verification flows for complex designs.
Implement scalable verification solutions using SystemVerilog, UVM, C++, Perl, and Python.
Track coverage metrics and identify/fix bugs during the pre-silicon validation process.
Apply advanced methodologies including constraint random verification and formal verification.
Develop reusable verification methodologies to support multi-platform hardware designs.
Partner with architecture and design teams to validate complex clocking and reset logic.

What we're looking for

BS or MS in EE/ECE or equivalent experience.
5+ years of relevant industry work experience.
Good understanding of Logic Design and Architecture.
Expertise in SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, and X prop.
Strong coding skills in SystemVerilog, C++, Perl, and Python.
Experience with block-level and system-level verification.
Prior experience implementing test plans for pre-silicon platforms.
Ability to develop scalable solutions and methodologies used by others.

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