Senior ASIC Verification Engineer

Nvidia

Remote

Quick summary

Work type
Remote
Location
Santa Clara, CA · Austin, TX
Salary
$136,000–$218,500 / yr
Posted
16 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $177k
$126k most similar roles pay here $228k

This role pays more than 53% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

The NVIDIA Clocks Team seeks a Senior ASIC Verification Engineer to own the validation of clocking structures in Tegra and GPU products, encompassing test plan development, automation, coverage metrics, bug identification, and productization. This role involves tackling complex verification challenges with scalable solutions across platforms using System Verilog, UVM, C++, Perl, Python, and NVIDIA’s custom tools. The ideal candidate will collaborate closely with the clocks architecture team to ensure high-quality design validation while coordinating with internal and external teams globally. Candidates should have a BS or MS in EE/ECE, 5+ years of industry experience, expertise in verification methodologies like SV constraint random verification, formal verification, and coverage metrics, as well as strong coding skills in System Verilog, Perl, Python, and C++.

What you'll do

  • Own validation of clocking structures in Tegra and GPU products throughout the entire development cycle.
  • Develop scalable verification solutions that work across different platforms.
  • Utilize System Verilog, UVM, C++, Perl, Python, and custom tools for verification tasks.
  • Create comprehensive test plans and execute them to ensure high-quality design coverage.
  • Collaborate with clocks architecture and design teams to validate clock designs effectively.

What we're looking for

  • 5+ years of relevant industry experience in ASIC verification.
  • Expertise in System Verilog, UVM, Formal Verification, coverage metrics, and profiling tools.
  • Strong coding skills in System Verilog, Perl, Python, and C++.
  • Experience in developing test plans for pre-silicon platforms.
  • Ability to collaborate with multiple groups across time zones.
  • Good understanding of logic design and architecture.
  • Exposure to block level and system-level verification.

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