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DDR Memory Tuning Signal Integrity Oscilloscopes Schematic Capture Board Design C C++ Java Python Perl Windows OS Linux Firmware +8 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification RTL Computer Architecture Testbench Development Regression Triage Coverage Closure Debug Caches Coherency Pipelines Arbitration Interconnect Networks Algorithms Data Structures +14 more Show less

Verilog RTL Python STA DRC LVS EM/IR Synthesis Physical Design Place and Route Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts +9 more Show less

Verilog RTL Physical Design STA DRC EM/IR Synthesis Python Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts +7 more Show less

System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal Network-on-Chip Regression Management +11 more Show less

Verilog System Verilog HDL Python Perl Ruby GPU Architecture SoC RTL Coding Cache On-chip Interconnect Data Compression Power Optimization Functional Simulation Debug +10 more Show less

GPU Architecture Micro-architecture Verilog System Verilog HDL RTL C++ Python Perl Ruby SoC Cache Memory Subsystem On-chip Interconnect Data Compression Architectural Modeling +11 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

ASIC Design 3D Memory Architecture RTL Verilog Verilog-A Verilog-AMS C C++ Python Perl Matlab EDA Tools HBM3/4 LPDDR PCIe UCIe Mixed-Signal Design Performance Modeling SoC Architecture DRAM FLASH SRAM +17 more Show less

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture +11 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification Constrained-Random Verification Coverage-Driven Verification LPDDR DDR HBM JEDEC UPF AXI APB AHB DFI RTL Simulation +15 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification SoC IC Package Scripting +5 more Show less

ASIC Design RTL DDR LPDDR PCDDR C C++ Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis x86 ARM Micro-architecture Logic Design +11 more Show less

ASIC Design 3D Memory Architecture RTL Verilog Verilog-A Verilog-AMS Python C++ Matlab Mixed-Signal Design SoC Architecture HBM3/4 LPDDR PCIe UCIe EDA Tools Performance Modeling DRAM FLASH SRAM +15 more Show less

Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture +9 more Show less

Memory Compiler SRAM Register-files ROM Circuit Design Python DFT Signal Integrity EM/IR Layout Integration Post-layout Simulation Verification +7 more Show less

VLSI Design SRAM Cadence Virtuoso SPICE FastSpice CMOS Layout Perl .tcl Java UNIX Monte-Carlo Physical Verification Circuit Design Memory Architecture AI Tools +10 more Show less

SRAM Register-files ROM Circuit Design Signal Integrity DFT Python Post-layout Simulation +3 more Show less

RTL Design Verilog SystemVerilog Python Perl Tcl Digital Logic Design Computer Architecture DDR LPDDR EDA Tools Lint CDC Timing Analysis Synthesis Simulation IP Microarchitecture +12 more Show less

HBM GDDR DRAM ASIC VLSI Mixed Signal Design Signal Integrity Linux Scripting Data Analysis Hardware Design Board Design ATE High-Performance Computing Artificial Intelligence +10 more Show less