Memory Circuit Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Rochester, MN
Employment
Full-time
Posted
48 days ago
Freshness
Confirmed live today
Closes
Feb 21, 2027

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Salary context

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Similar $204k
$142k $265k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $172,000–$236,262.

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Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 241 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 161 roles with salary data.

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At a glance

TL;DR · Memory Circuit Design Engineer

Memory Circuit Design Engineer-MN Rochester will join the Central Engineering Group as part of an elite memory team. The role involves developing memory compilers and custom macros on bleeding edge process technology. Key responsibilities include analyzing memory architectures, designing circuit blocks at the gate or transistor level, and performing post-layout simulations and verification. The engineer will floorplan physical implementations, integrate characterization flows to extract timing and power information, and develop automation scripts. Required skills include deep knowledge of transistor level circuit behavior, device physics, signal integrity, EM/IR, and reliability analysis. Candidates must understand SRAMs, Register-files, Multi-ports, and ROM. Proficiency in Python, transistor level simulators, and DFT schemes is required to solve complex memory modeling and silicon debugging problems within the memory product area.

What you'll do

  • Analyze different memory architectures and highlight the technical tradeoffs.
  • Design and build memory or circuit blocks at the gate or transistor level.
  • Simulate and analyze circuit designs using transistor level simulators.
  • Extract layouts and perform post-layout simulations and verification.
  • Floorplan physical implementation and leafcell layout integration to build physical macros.
  • Develop scripts to automate characterization flows, simulations, and verification.
  • Specify and verify various behavioral and physical memory models.
  • Specify silicon test plans and correlate silicon data to simulation results.

What we're looking for

  • BS in Electrical Engineering.
  • 8+ years of related experience.
  • Strong knowledge in development of memory compilers or custom digital circuits like SRAMs, Register-files, Multi-ports, and ROM.
  • Deep understanding of transistor level circuit behavior and device physics.
  • Good understanding of signal integrity, EM/IR, and reliability analysis.
  • Understanding of memory behavioral and physical models.
  • Understanding of DFT schemes and chip level integration.
  • Proficiency in running simulators, writing automation scripts, and tools savvy.
  • Familiarity with test setups, silicon testing, and debug (preferred).
  • Proficiency in Python programming language (preferred).

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