Design Verification Engineer, Memory Subsystem

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $159,600–$239,400 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k

This role $200k

$134k $251k

below market most similar roles pay here above market

This role pays more than 57% of similar roles. Most pay $168,500–$222,500 — the blue band above. At the midpoint, this role pays about $200k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer, Memory Subsystem

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The Design Verification Engineer — Memory Subsystem joins the memory subsystem verification team to develop and execute comprehensive verification strategies for complex digital designs. This role involves the complete verification lifecycle, including developing verification plans, creating UVM-based testbenches, and driving functional and code coverage closure. The engineer will build and maintain reusable SystemVerilog and UVM environments, develop components like sequences, drivers, monitors, and scoreboards, and write SystemVerilog Assertions for protocol and timing verification. Key technical requirements include proficiency in Verilog, SystemVerilog, UVM, and SystemVerilog Assertions. The work focuses on verifying memory controllers, PHY-related logic, and high-performance memory subsystems, specifically addressing DDR, LPDDR, HBM, and JEDEC specifications to ensure functional correctness across multiple operating modes and multi-clock-domain designs.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification Constrained-Random Verification Coverage-Driven Verification LPDDR DDR HBM JEDEC UPF AXI APB AHB DFI RTL Simulation

What you'll do

Develop verification strategies, test plans, and coverage plans for complex RTL designs.
Build and maintain reusable SystemVerilog/UVM environments including sequences, drivers, monitors, and scoreboards.
Create and execute constrained-random, directed, error-injection, and corner-case tests.
Write and maintain SystemVerilog Assertions for protocol, interface, timing, and functional verification.
Verify memory-controller, PHY-interface, and memory-subsystem functionality across multiple operating modes.
Analyze simulation failures and perform root-cause analysis using waveform viewers and transaction databases.
Review RTL, microarchitecture specifications, and design changes for functional correctness and verifiability.
Drive functional, code, assertion, and coverage closure for high-performance memory subsystems.

What we're looking for

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, or integration experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, or integration experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, or integration experience.
3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
Strong hands-on experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
Experience developing and debugging reusable UVM-based verification environments and components like sequences, drivers, and monitors.
Experience with constrained-random verification, coverage-driven verification, and writing assertions for protocol compliance.
Experience verifying LPDDR, DDR, DDR PHY, HBM, or custom memory interfaces (preferred).

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