GPU Design Engineer, Memory Hierarchy

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$150,400–$277,600 / yr
Posted
24 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $206k
This role $214k
$135k $293k
below market most similar roles pay here above market

This role pays more than 64% of similar roles. Most pay $177,050–$235,750 — the blue band above. At the midpoint, this role pays about $214k versus about $206k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3595 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2772 roles with salary data.

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At a glance

TL;DR · GPU Design Engineer, Memory Hierarchy

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As a GPU Design Engineer – Memory Hierarchy within the Silicon Technologies group, you will contribute to the design and manufacture of a next-generation, high-performance, and power-efficient system-on-chip. Your primary responsibilities include participating in micro-architecture specification and RTL coding while exploring critical architecture trade-offs regarding performance, area, and power consumption. You will collaborate with the verification team for functional simulation and debug tasks. The role requires proficiency in Verilog, System Verilog, and HDL, along with experience in scripting languages like Perl, Python, and Ruby. You must possess knowledge of CPU or GPU architecture, specifically in areas such as cache, on-chip interconnect networks, data compression, or GPU pipelines. You will solve complex technical problems involving timing and power optimization for high-performance, low-power designs.

Skills

Verilog System Verilog HDL Python Perl Ruby GPU Architecture SoC RTL Coding Cache On-chip Interconnect Data Compression Power Optimization Functional Simulation Debug

What you'll do

  • Participate in micro-architecture specification for next-generation high-performance processors.
  • Write RTL code using Verilog, System Verilog, or other HDLs.
  • Analyze and explore architecture trade-offs regarding performance, area, and power consumption.
  • Perform timing and power optimizations for GPU designs.
  • Collaborate with the verification team to conduct functional simulations and debug issues.
  • Debug complex performance issues within the GPU memory hierarchy.
  • Develop solutions for cache, on-chip interconnect networks, or data compression.

What we're looking for

  • Minimum of a BS degree and 3+ years of relevant experience.
  • Experience and knowledge of CPU or GPU architecture.
  • Experience in cache, on-chip interconnect network, data compression, or GPU pipeline.
  • Experience in timing and power optimization.
  • Proficiency in Verilog/System Verilog and HDL.
  • Knowledge of high performance, low power designs (preferred).
  • Experience in debugging performance issues (preferred).
  • Experience with scripting languages such as Perl, Python, and Ruby (preferred).

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