Hardware Design Validation Engineer, Memory Subsystem

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$108,000–$184,000 / yr
Employment
Full-time
Posted
2 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $146k
$95k $233k
below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $152,875–$216,250 — the blue band above. At the midpoint, this role pays about $146k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1472 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1109 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Hardware Design Validation Engineer, Memory Subsystem

JOB TITLE: Hardware Design Validation Engineer - Memory Subsystem - New College Grad 2026 The System Product Team is seeking a Hardware Design Validation Engineer - Memory Subsystem - New College Grad 2026 to manage the GPU memory subsystem from first silicon power-on to production. This role involves planning and performing DDR memory tuning, validation, and feature enablement. You will review silicon design specifications, component datasheets, board schematics, and layouts to inform engineering decisions. You will debug controller, memory, board, and software/firmware level issues using digital, analog, and computer design knowledge. Required skills include high-speed signal integrity, oscilloscope experience, schematic capture, and board design. Candidates should possess working knowledge of PC systems, Windows OS, and Linux, along with proficiency in C, C++, Java, Python, or Perl to solve complex memory subsystem problems.

What you'll do

  • Plan and perform DDR memory tuning, validation, and feature enablement on NVIDIA products.
  • Review silicon design specifications, component datasheets, board schematics, and layouts to inform engineering decisions.
  • Debug and resolve controller, memory, board, and software/firmware level issues across the product lifecycle.
  • Apply digital, analog, and computer design knowledge to troubleshoot hardware and software problems.
  • Refine memory bringup and validation strategies by providing feedback to silicon, board, and software teams.
  • Work directly with silicon, board, and firmware teams to shape product performance from the ground up.

What we're looking for

  • Completed a BS or MS in Electrical Engineering or a related field, or equivalent experience.
  • 2+ years of relevant experience, including internships, co-ops, or research projects.
  • Understanding of high-speed signal integrity and hands-on experience with oscilloscopes.
  • Familiarity with schematic capture and board design.
  • Working knowledge of PC systems, Windows OS, and Linux.
  • Strong grasp of EE fundamentals with the ability to break down complex problems using first principles.
  • Familiarity with scripting or programming languages such as C, C++, Java, Python, or Perl.
  • Experience as a tutor or teaching assistant in an engineering or technical subject (preferred).

More like this

Similar roles

Hardware Design Validation Engineer, Memory Subsystem

Nvidia

Santa Clara, CA 101 days ago $108,000–$184,000
DDR Memory Tuning Mixed Signal Digital Design Embedded Systems Signal Integrity Schematic Capture Board Design C C++ Java Python Perl Linux Windows OS Oscilloscopes High-Performance Computing Firmware
2+ yrs exp

ASIC Design Engineer

Nvidia

Santa Clara, CA 94 days ago $100,000–$166,750
RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis VLSI Design C++ Python Perl Computer Architecture DMA Engines Bus Protocols Interconnect Networks Caches Digital Systems

ASIC Verification Engineer, Memory Management

Nvidia

Durham, NC +2 13 days ago $100,000–$166,750
SystemVerilog C C++ UVM ASIC Design Verification Methodology Constrained Random Testing Assertion-Based Verification Python Perl VCS IES GDB Debussy Computer Architecture Memory Management Object Oriented Programming Functional Coverage

Post-Silicon Memory Subsystem Validation Engineer

Amd

Austin, TX +1 12 days ago $133,200–$199,800
DDR5 LPDDR5x Post-Silicon Validation First-Silicon Bring-up Root-Cause Analysis Memory Subsystems Firmware Software Pre-silicon Validation Lab Equipment AI Automation

Design Verification Engineer, Memory Subsystem

Qualcomm

Santa Clara, CA 24 days ago $159,600–$239,400
SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification Constrained-Random Verification Coverage-Driven Verification LPDDR DDR HBM JEDEC UPF AXI APB AHB DFI RTL Simulation
4+ yrs exp