Principal 3D Memory Chip Architect and Design Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $192,000–$288,000 / yr
Posted: 16 days ago
Freshness: Confirmed live 2 days ago
Closes: Feb 22, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k

This role $240k

$146k most similar roles pay here $303k

This role pays more than 78% of similar roles. Most pay $177,250–$235,750 — the shaded band above. At the midpoint, this role pays about $240k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Principal 3D Memory Chip Architect and Design Engineer

Role Posting Log in to save

3D Memory Chip Architect and Design, Principal Engineer joins the Custom Memory Team within the Process & Package Solutions Group to develop memory-centric compute systems for data center, mobile, compute, and XR applications. The role involves assessing and optimizing 3D Memory architectures to improve bandwidth, latency, power, thermal, and area efficiency while exploring near-memory processing units and interconnecting memory cubes using scale-up and scale-out fabrics. Key responsibilities include developing and validating models for performance and yield, designing power distribution topologies, floorplanning chips under manufacturing constraints, and creating novel fabrics for high-bandwidth data distribution. The position requires expertise in RTL, circuit and system design, SoC architecture, and memory circuit design. Candidates should be proficient in EDA tools, Matlab, and Python or C/C++, with specific knowledge of UCIe, UAL, LPDDR, HBM3/4, and PCIe interfaces to solve complex 3D integration challenges.

Skills

3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS C C++ Python Perl Matlab EDA Tools HBM3/4 LPDDR PCIe UCIe UAL SRAM DRAM FLASH 2.5D/3D Integration

What you'll do

Optimize 3D DRAM/FLASH organization and near-memory computing architectures for high density and power efficiency.
Develop and validate models for 3D memory performance, power, and yield based on bank and TSV choices.
Design novel fabrics to distribute high-bandwidth data from 3D memory arrays to near-memory computing units.
Create power distribution topologies that ensure robust operation within 3D stacks.
Simulate and emulate system performance of 3D memory architectures across AI, compute, and mobile workloads.
Floorplan 3D memory chips and design control structures under manufacturing, testability, and repairability constraints.

What we're looking for

Bachelor's degree with 8+ years of experience, Master's with 7+ years, or PhD with 6+ years in ASIC design, verification, validation, or integration.
Experience in RTL, circuit, and system design to model and optimize dataflow.
Experience in SoC architecture and power, clock, and bus design.
Experience in DRAM/FLASH architecture performance assessment and memory circuit design.
Proficiency in programming languages such as C, C++, Python, or scripting languages like Perl.
Ability to develop Verilog, Verilog-A, or Verilog-AMS models of critical dataflow.
Knowledge of memory architecture, buses, 2.5D/3D integration, and interfaces like UCIe, UAL, LPDDR, HBM3/4, and PCIe.
Proficiency in EDA tools, Matlab, and Python for performance modeling and design.

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