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Based on 240 similar postings.
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About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
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575 open roles
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Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
JOB TITLE: 3D Memory Chip Architect and Design, Principal Engineer
The Principal Engineer joins the Custom Memory Team within the Process and Package Solutions Group to design 3D memory architectures for memory-centric compute systems. This role focuses on optimizing 3D DRAM and FLASH organizations to improve bandwidth, latency, power, and thermal efficiency for data center, mobile, compute, and XR applications. Key responsibilities include developing models for performance and yield, designing power distribution topologies, and floorplanning 3D memory chips under manufacturing constraints. The candidate will utilize skills in RTL, circuit design, and performance modeling to develop novel fabrics for high-bandwidth data distribution. Required technical knowledge includes memory bank organization, signaling, and 3D integration. Proficiency in tools like Matlab and Python, along with experience in UCIe, UAL, LPDDR, HBM3/4, and PCIe, is essential for this work.
Develop and optimize 3D DRAM/FLASH organization and near-memory computing architectures for high density and efficiency.
Develop and validate models for 3D memory performance, power, and yield based on bank and TSV choices.
Design novel fabrics to distribute high-bandwidth data from 3D memory arrays to near-memory computing units.
Develop power distribution topologies to ensure robust memory operation within 3D stacks.
Simulate and emulate system performance of 3D memory architecture choices across AI, compute, and mobile workloads.
Floorplan 3D memory chips and design array control structures under manufacturing and thermal constraints.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Experience in RTL, circuit and system design to model and optimize dataflow (preferred).
Experience in SoC architecture and power/clock/bus design (preferred).
Experience in DRAM/FLASH architecture performance assessment (preferred).
Experience in memory circuit design (SRAM/DRAM/FLASH/ROM/OPT, etc) (preferred).
Experience in programming languages (C/C++/Python) or scripting languages (Perl/Python) (preferred).
Remote (Santa Clara, CA)+336 days ago
$184,000–$287,500
GPU Architecture
Memory Systems
CUDA
PPA) analysis
RTL Simulation
Emulation
Verilog
VHDL
C
C++
Ansys Power Artist
Synopsys PTPX
Hardware Design
Scripting Languages