Principal Engineer, System Power for Advanced 2.5D/3D High-Performance Compute

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$192,000–$288,000 / yr
Posted
3 days ago
Closes
Dec 27, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $207k
This role $240k
$149k most similar roles pay here $303k

This role pays more than 78% of similar roles. Most pay $177,287–$235,750 — the shaded band above. At the midpoint, this role pays about $240k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 533 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 513 roles with salary data.

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At a glance

TL;DR · Principal Engineer, System Power for Advanced 2.5D/3D High-Performance Compute

Role Posting Log in to save

The Qualcomm Memory Design/Technology Team is seeking a senior-level engineer to join their System PDN and power modeling group, where the candidate will assess and optimize high-performance chip and across-chiplet PDN architecture for robust computing and low-noise performance in applications like cloud, compute, mobile, and IoT. Day-to-day responsibilities include developing and validating models for power density under various workloads, identifying critical power scenarios within packaging constraints, and simulating system power behavior on different scenarios. The role requires expertise in EDA tools such as Voltus, Redhawk, SPICE, and Virtuoso, along with knowledge of signal and power integrity, chiplets, PMIC architecture, and thermal modeling. Candidates should have a Master's or Ph.D. in Electrical Engineering and experience in PDN optimization, decoupling capacitance placement, and power modeling for high-performance computing systems.

Skills

Voltus Redhawk SPICE Virtuoso C C++ Python Perl IBIS Verilog-A RLC networks EDA tools Power Integrity Signal Integrity Chiplets PMIC architecture Thermal Modeling High-Frequency Signal Assessment Model Order Reduction

What you'll do

  • Develop and optimize PDN memory and computing architectures for high-performance applications.
  • Validate power and power density models under various workloads for multiple modules.
  • Identify critical power scenarios and propose solutions within packaging constraints.
  • Simulate system power behavior across different operational states using EDA tools.
  • Floorplan 2.5/3D PDN designs considering manufacturing, testability, and performance factors.
  • Develop and utilize optimal control mechanisms for power switches in chip design.

What we're looking for

  • Experience in PDN and power modeling for high-performance chips.
  • Proficiency in EDA tools like Voltus, Redhawk, SPICE, Virtuoso.
  • Knowledge of signal and power integrity, chiplets, and PMIC architecture.
  • Ability to develop models for power density under various workloads.
  • Familiarity with thermal modeling and hotspot mitigation techniques.

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