Principal 3D Memory Chip Architect and Design Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $192,000–$288,000 / yr
Posted: 73 days ago
Freshness: Confirmed live yesterday
Closes: Dec 27, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k

This role $240k

$146k most similar roles pay here $303k

This role pays more than 78% of similar roles. Most pay $177,250–$235,750 — the shaded band above. At the midpoint, this role pays about $240k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Principal 3D Memory Chip Architect and Design Engineer

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As a 3D Memory Chip Architect and Design, Principal Engineer on the Custom Memory Team, you will design and optimize 3D memory architectures for data center, mobile, compute, and XR systems. You will be responsible for developing and validating models for performance, power, and yield while designing novel fabrics to distribute high-bandwidth data from 3D DRAM arrays to near-memory computing units. Your daily work involves floorplanning chips under manufacturing constraints, designing memory array control structures, and developing power distribution topologies. The role requires expertise in advanced packaging, 3D integration, and technologies including UCIe, UAL, LPDDR, HBM3/4, and PCIe. You will utilize tools such as Matlab and Python while applying skills in RTL, circuit design, and SoC architecture to solve complex problems regarding memory-centric compute systems and high-density, high-efficiency hardware integration.

Skills

3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS SoC Architecture HBM3/4 LPDDR PCIe UCIe Python C++ Matlab EDA Tools Mixed-Signal Design Performance Modeling

What you'll do

Optimize 3D DRAM/FLASH organization and near-memory computing architectures for high density and efficiency.
Develop and validate models for 3D memory performance, power, and yield based on bank and TSV choices.
Design novel fabrics to distribute high-bandwidth data from 3D memory arrays to near-memory computing units.
Create power distribution topologies that ensure robust operation within 3D stacks.
Simulate and emulate system performance of 3D memory architectures across AI, compute, and mobile workloads.
Floorplan 3D memory chips and design control structures under manufacturing, testability, and repairability constraints.

What we're looking for

Bachelor's degree with 8+ years of experience, Master's with 7+ years, or PhD with 6+ years in ASIC design, verification, validation, or integration.
Experience in RTL, circuit, and system design to model and optimize dataflow.
Experience in SoC architecture and power, clock, and bus design.
Experience in DRAM/FLASH architecture performance assessment and memory circuit design.
Proficiency in programming languages such as C, C++, Python, or scripting languages like Perl.
Ability to develop Verilog, Verilog-A, or Verilog-AMS models of critical dataflow.
Knowledge of memory architecture, buses, 2.5D/3D integration, and interfaces like UCIe, UAL, LPDDR, HBM3/4, and PCIe.
Proficiency in EDA tools, Matlab, and Python for performance modeling and design.

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