Memory Control Design Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $121,800–$182,600 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $152k

$108k $254k

below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $171,125–$229,612 — the blue band above. At the midpoint, this role pays about $152k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Memory Control Design Engineer

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The Memory Control Design Engineer joins the QCT Memory Controller Design Team to develop next-generation high-speed DDR controllers. This role involves the architecture, design, and deployment of Memory Controllers for LPDDR and PCDDR technologies into products. Key responsibilities include developing design specifications, driving micro-architecture for logic design, and implementing RTL. The engineer must debug designs, provide integration support, and perform synthesis, timing closure, physical design support, gate level simulations, and power analysis. Technical requirements include experience with DDR controller architectures, specifically front-end interfaces for CPU, DSP, and multimedia processors, as well as x86 or ARM CPU/bus architectures. Additionally, the candidate will participate in C/C++ modeling of memory controller IP and contribute to improving overall design methodology to enhance productivity and quality.

Skills

ASIC Design RTL DDR LPDDR PCDDR C C++ Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis x86 ARM Micro-architecture Logic Design

What you'll do

Develop and contribute to design specifications for LPDDR/PCDDR memory controllers.
Drive the micro-architecture for portions of the logic design.
Implement and deliver high-quality RTL for high-speed DDR controllers.
Perform synthesis, timing closure, and physical design support.
Conduct gate level simulations and power analysis for designs.
Participate in C/C++ modeling of memory controller IP.
Debug designs and provide debug support for integrated chip components.
Improve design methodologies to increase productivity and quality of results.

What we're looking for

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
3-8 years of experience.
Experience with DDR controller architectures, especially the front end interfacing to the CPU, DSP, and multimedia processors.
Experience with x86 or ARM CPU/bus architectures.
Ability to implement RTL, perform synthesis, timing closure, physical design support, gate level simulations, and power analysis.
Ability to participate in C/C++ modeling of memory controller IP.

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