Memory Control Design Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $115,600–$173,400 / yr
Posted: 59 days ago
Freshness: Confirmed live yesterday
Closes: Jan 10, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $197k

This role $144k

$102k most similar roles pay here $244k

This role pays less than 92% of similar roles. Most pay $169,500–$224,175 — the shaded band above. At the midpoint, this role pays about $144k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Memory Control Design Engineer

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Memory Control Design Engineer The Memory Controller Design Team is seeking an ASIC Design Engineer to work on the next generation of high speed DDR Controllers. This role involves the architecture, design, and deployment of memory controllers for LPDDR and PCDDR technologies within products. The engineer will be responsible for developing design specifications, driving micro-architecture for logic design portions, and implementing RTL while collaborating with verification engineers to ensure high quality designs. Key responsibilities include debugging designs during integration, performing synthesis, timing closure, physical design support, gate level simulations, and power analysis. Additionally, the role involves C/C++ modeling of memory controller IP and improving design methodology. The position requires expertise in DDR controller architectures interfacing with CPU, DSP, and multimedia processors, as well as experience with x86 or ARM CPU and bus architectures to enable high speed designs.

Skills

ASIC Design RTL DDR LPDDR PCDDR x86 ARM C C++ Synthesis Timing Closure Gate Level Simulation Power Analysis Micro-architecture Logic Design

What you'll do

Develop design specifications and drive the micro-architecture for high-speed memory controller logic.
Implement and deliver RTL for LPDDR/PCDDR technologies integrated into Qualcomm products.
Debug designs and provide technical support when components are integrated into the full chip.
Perform synthesis, timing closure, physical design support, and gate level simulations.
Conduct power analysis to ensure high-quality design results.
Participate in C/C++ modeling of memory controller IP.
Contribute to improvements in design methodology to increase productivity and quality.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design experience.
Master's degree in Science, Engineering, or a related field with 1+ year of ASIC design experience.
PhD in Science, Engineering, or a related field.
Experience with DDR controller architectures, specifically front ends interfacing to CPU, DSP, and multimedia processors.
Experience with x86 or ARM CPU/bus architectures.
3-8 years of relevant professional experience.
Proficiency in RTL implementation, synthesis, timing closure, and physical design support.
Ability to perform C/C++ modeling of memory controller IP.

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