Digital ASIC Design Engineer
Qualcomm
At a glance
AI generatedThe ASIC Design Engineer role at Qualcomm Technologies Inc.'s Memory Controller Design Team involves developing high-speed DDR controllers for QCT products, focusing on the front-end interface with CPUs, DSPs, and multimedia processors. The candidate will be responsible for designing and implementing RTL code, collaborating closely with verification engineers to ensure high-quality designs, and conducting synthesis, timing closure, and physical design support tasks. Key responsibilities include debugging designs both independently and in collaboration with other teams during integration phases, as well as contributing to C/C++ modeling of memory controller IP. The ideal candidate has 3-8 years of experience with DDR controller architectures and familiarity with x86 or ARM CPU/bus architectures, aiming to enhance design methodologies for improved productivity and quality results within a large-scale semiconductor environment.
Skills
What you'll do
What we're looking for
Market check
This $115,600–$173,400 range sits above 18% of similar postings on FindRole.
Peer median band
$148,300–$221,800
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$156,000–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 569 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.
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