Lead Design Verification Engineer, Memory Controller

Amd

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $200,000–$300,000 / yr
Posted: 16 days ago
Freshness: Confirmed live 2 days ago
Closes: Sep 22, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k

This role $250k

$132k most similar roles pay here $318k

This role pays more than 83% of similar roles. Most pay $177,250–$235,562 — the shaded band above. At the midpoint, this role pays about $250k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 487 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 487 roles with salary data.

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At a glance

TL;DR · Lead Design Verification Engineer, Memory Controller

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Lead Design Verification Engineer-Memory Controller The Adaptive and Embedded Computing Group seeks a Senior Staff Silicon Design Verification Engineer to provide technical leadership in the verification of cutting-edge DRAM Memory Controller IPs, high-speed Crypto, and Network-on-Chip. You will architect, develop, and utilize simulation and formal-based verification environments at both block and SoC levels to ensure first-pass silicon success. Responsibilities include managing teams through planning, execution, and delivery while developing comprehensive testbenches and test cases. The role requires expertise in UVM, SystemVerilog, assertion-based verification, and metric-driven verification. You will work with tools like Synopsys VCS, Cadence Xcelium, and formal property checking tools such as JasperGold or Questa Formal. This position focuses on the technical challenges of high-speed memory protocols including DDR5, LPDDR6, and HBM4, while addressing complex issues like board skew, jitter modeling, and power-aware verification for high-performance VLSI designs.

Skills

UVM System Verilog Formal Verification Assertion-Based Verification Synopsys VCS Cadence Xcelium JasperGold Questa Formal Gate-Level Simulation Power-Aware Verification DDR5 LPDDR6 HBM4 Network-on-Chip NoC VLSI Silicon Debug

What you'll do

Lead the verification of high-speed Crypto, Network-on-Chip (NoC), and advanced DRAM Memory Controller IPs.
Architect and develop simulation and formal-based verification environments at both block and SoC levels.
Manage verification teams through planning, execution, tracking, and final delivery to programs.
Develop comprehensive verification plans including specific testbenches and test cases.
Implement advanced verification methodologies such as UVM, formal verification, and assertion-based verification.
Mentor and guide junior engineers to foster a collaborative and innovative team environment.
Define and establish verification methodologies, tools, and infrastructure for high-performance VLSI designs.

What we're looking for

Hold a BS with 8+ years, MS with 6+ years, or PhD with 3+ years in Electrical Engineering, Computer Engineering, or Computer Science.
Experience with verification of state-of-the-art memory controllers (DDR, LPDDR, HBM) and understanding of protocols and calibration is required.
Proven track record in technical leadership of teams with 5+ engineers including planning, execution, tracking, and delivery.
Experience developing UVM and SystemVerilog test benches using simulation tools like Synopsys VCS or Cadence Xcelium is required.
Strong understanding of verification techniques, including assertion and metric-driven verification, is required.
Experience as a verification architect establishing methodology, tools, and infrastructure for high-performance IP or VLSI designs (preferred).
Experience with formal property checking tools such as VC Formal, JasperGold, or Questa Formal (preferred).
Experience with gate-level simulation, power-aware verification, or silicon debug at the tester and board level (preferred).

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