Memory System Designer and Place and Route Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Mendota Heights-Northland
Salary
$109,700–$175,500 / yr
Employment
Full-time
Posted
6 days ago
Freshness
Confirmed live today
Closes
Apr 2, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $195k
This role $143k
$95k $250k
below market most similar roles pay here above market

This role pays less than 85% of similar roles. Most pay $159,387–$231,475 — the blue band above. At the midpoint, this role pays about $143k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 241 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 161 roles with salary data.

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At a glance

TL;DR · Memory System Designer and Place and Route Engineer

Role Posting Log in to save

The Memory System Designer and Place and Route Engineer will join the Central Engineering Group as part of the memory subsystem design team. This role focuses on the development of large memory blocks and subsystems. Key responsibilities include architecting and designing memory subsystems, implementing RTL of subsystem designs, and performing physical design tasks such as place and route. The engineer must achieve design closure for timing, DRC, LVS, and EM/IR while performing gate netlist synthesis. Required technical skills include writing and debugging Verilog RTL code, running STA and synthesis tools, and using Python for automation scripts. Candidates must also be capable of running logical equivalency checkers and possess a good understanding of memory behavior to solve complex hardware design problems.

Skills

Verilog RTL Python STA DRC LVS EM/IR Synthesis Physical Design Place and Route Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts

What you'll do

  • Architect and design complex memory subsystems and large memory blocks.
  • Implement RTL for subsystem designs using Verilog.
  • Perform physical design tasks including placement and routing.
  • Achieve design closure for timing, DRC, LVS, and EM/IR requirements.
  • Execute gate netlist synthesis and run synthesis tools.
  • Run and debug logical equivalency checkers.
  • Write automation scripts and tools using Python.

What we're looking for

  • Minimum of 8 years of relevant experience.
  • Bachelor in Electrical Engineering.
  • Strong design skills including the ability to write and debug Verilog RTL code.
  • Place and route expertise.
  • Proficiency in running STA, DRC, EM/IR tools, and attaining design closure.
  • Ability to code in Python.
  • Good understanding of synthesis tools and running synthesis.
  • Capable of running and debugging logical equivalency checkers.

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