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Verilog RTL Physical Design STA DRC EM/IR Synthesis Python Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts +7 more Show less

Python TCL LangGraph LLM RAG Docker Kubernetes Vector Databases REST APIs Microservices System Verilog UVM EDA Tool S Synopsys Cadence Siemens EDA Model Context Protocol (MCP) +12 more Show less

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces +10 more Show less

Memory PHY LPDDR DDR GDDR HBM SerDes Verilog SystemVerilog Python Perl Tcl RTL Mixed-Signal Integration Static Timing Analysis Synthesis UPF Power Optimization Silicon Bring-up Firmware Integration +14 more Show less

DDR Memory Tuning Signal Integrity Oscilloscopes Schematic Capture Board Design C C++ Java Python Perl Windows OS Linux Firmware +8 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting +3 more Show less

ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA +12 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification RTL Computer Architecture Testbench Development Regression Triage Coverage Closure Debug Caches Coherency Pipelines Arbitration Interconnect Networks Algorithms Data Structures +14 more Show less

Verilog RTL Python STA DRC LVS EM/IR Synthesis Physical Design Place and Route Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts +9 more Show less

UVM System Verilog Formal Verification Python PCIe CXL AMBA CHI JEDEC Memory Controller IP Verification Generative AI Simulation SVTB +9 more Show less

System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal Network-on-Chip Regression Management +11 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

Verilog System Verilog HDL Python Perl Ruby GPU Architecture SoC RTL Coding Cache On-chip Interconnect Data Compression Power Optimization Functional Simulation Debug +10 more Show less

GPU Architecture Micro-architecture Verilog System Verilog HDL RTL C++ Python Perl Ruby SoC Cache Memory Subsystem On-chip Interconnect Data Compression Architectural Modeling +11 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

ASIC Design 3D Memory Architecture RTL Verilog Verilog-A Verilog-AMS C C++ Python Perl Matlab EDA Tools HBM3/4 LPDDR PCIe UCIe Mixed-Signal Design Performance Modeling SoC Architecture DRAM FLASH SRAM +17 more Show less

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture +11 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification Constrained-Random Verification Coverage-Driven Verification LPDDR DDR HBM JEDEC UPF AXI APB AHB DFI RTL Simulation +15 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification SoC IC Package Scripting +5 more Show less

ASIC Design SRAM Schematic Capture Layout Planning FinFET CMOS SoC PPA L1/L2 Cache Register File Physical Implementation +6 more Show less