Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Memory Design Remove filter Clear all

13 of up to 20 (filtered)

High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 8 days ago $140,000–$229,800
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture
4+ yrs exp
Save

Principal 3D Memory Chip Architect and Design Engineer

Qualcomm

San Diego, CA 16 days ago $192,000–$288,000
Actively hiring Confirmed live 2 days ago High trust Above market
3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS C C++ Python Perl Matlab EDA Tools HBM3/4 LPDDR PCIe UCIe UAL SRAM DRAM FLASH 2.5D/3D Integration
8+ yrs exp
Save

Design Verification Engineer, DDR Memory Subsystem

Microsoft

25 days ago $102,100–$202,200
Actively hiring Confirmed live 2 days ago Trusted Below market
UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI JEDEC Memory Controller Generative AI Verification Methodology
2+ yrs exp
Save

Design Verification Engineer, Memory Subsystem

Qualcomm

Santa Clara, CA 25 days ago $153,200–$229,800
Actively hiring Confirmed live yesterday Trusted Competitive pay
SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification UPF AXI APB AHB DFI JEDEC DDR LPDDR HBM Constrained-Random Verification Coverage-Driven Verification Simulation Waveform Analysis
4+ yrs exp
Save

High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 30 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
Save

High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 37 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
Save

Staff Memory Controller Architecture and Design Engineer

Qualcomm

San Diego, CA 43 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC
4+ yrs exp
Save

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 43 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Low trust Below market
Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems
4+ yrs exp
Save

Memory Control Design Engineer

Qualcomm

San Diego, CA 59 days ago $115,600–$173,400
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL DDR LPDDR PCDDR x86 ARM C C++ Synthesis Timing Closure Gate Level Simulation Power Analysis Micro-architecture Logic Design
2+ yrs exp
Save

Memory Designer

Qualcomm

San Diego, CA 71 days ago $164,000–$246,000
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design SRAM Layout Planning Schematic Capture Simulation FinFET CMOS SoC Digital Circuits Register File Verification Validation
6+ yrs exp
Save

Principal 3D Memory Chip Architect and Design Engineer

Qualcomm

San Diego, CA 73 days ago $192,000–$288,000
Actively hiring Confirmed live yesterday High trust Above market
3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS SoC Architecture HBM3/4 LPDDR PCIe UCIe Python C++ Matlab EDA Tools Mixed-Signal Design Performance Modeling
8+ yrs exp
Save

Memory Subsystem Architect and Design Engineer

Amd

Santa Clara, CA 99 days ago $232,000–$348,000
Actively hiring Confirmed live 2 days ago High trust Above market
DDR5 DDR4 Memory Subsystems ASIC Altium Cadence SPICE Python Root Cause Analysis Protocol Analyzers Circuit Design System Integration
Hybrid
Save

Senior Design Verification Engineer, GPU Memory Subsystem

Nvidia

Durham, NC 144 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Low trust Competitive pay
System Verilog Verilog UVM Python C++ ASIC Verification Pre-silicon Testbench Development Computer Architecture Arbitration Scripting Data Structures Algorithms RTL Performance Verification
5+ yrs exp
Save