below marketmost similar roles pay hereabove market
This role pays more than
92%
of similar roles. Most pay
$182,000–$254,750
— the blue band above.
At the midpoint, this role pays about
$290k
versus about
$218k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
510 open roles
on FindRole.
Listed pay typically runs
$172,000–$258,000
across 510 roles with salary data.
The Memory PHY Architect joins the Memory PHY team to architect and develop high-speed memory interface IP. This role involves shaping digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies. Key responsibilities include defining product features, translating microarchitecture requirements into technical specifications, and leading development from pathfinding through RTL implementation and physical realization. The architect drives analog and digital co-design, firmware integration, synthesis, static timing analysis, and power optimization to meet specific power, performance, and area targets. Required expertise includes Memory PHY architecture, SerDes, and memory controllers. Candidates must demonstrate proficiency in Verilog, SystemVerilog, and scripting languages like Python, Perl, or Tcl. The role solves complex technical issues across IP boundaries to ensure high-speed memory interface functionality and silicon bring-up success.
Translate architecture and microarchitecture requirements into technical specifications and product features.
Lead Memory PHY digital architecture development from pathfinding through RTL implementation and physical realization.
Architect and implement PHY link-layer functionality in partnership with analog and system architects.
Drive analog and digital co-design, RTL coding, and firmware integration for high-speed memory interfaces.
Guide synthesis, static timing analysis, and power optimization to achieve specific power, performance, and area targets.
Identify complex technical risks across IP boundaries and drive architectural solutions to meet requirements.
Support post-silicon teams in debugging and resolving functional, performance, and power issues.
Advance AI-assisted design and verification methodologies to improve engineering efficiency and design quality.
What we're looking for
Lead Memory PHY digital architecture development from pathfinding and microarchitecture through RTL implementation, verification, and physical realization.
Architect and implement PHY link-layer functionality in partnership with analog and system architects.
Drive analog and digital co-design, digital logic development, RTL coding, and firmware integration for high-speed memory interfaces.
Guide synthesis, static timing analysis, timing closure, power optimization, and physical implementation to achieve power, performance, and area targets.
Support post-silicon teams in debugging and resolving functional, performance, and power issues.
Deep expertise in Memory PHY architecture and implementation, including LPDDR, DDR, GDDR, HBM, SerDes, memory controllers, or other high-speed I/O subsystems (preferred).
Expert proficiency in Verilog or SystemVerilog, digital design methodologies, and scripting languages such as Python, Perl, or Tcl (preferred).
A bachelor’s, master’s, or doctoral degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (preferred).