Design Verification Engineer, DDR Memory Subsystem

Microsoft

Confirmed live today Trusted
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$102,100–$202,200 / yr
Posted
27 days ago
Freshness
Confirmed live today
Closes
Mar 29, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $152k
$87k $245k
below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $168,500–$224,075 — the blue band above. At the midpoint, this role pays about $152k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 694 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 651 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Design Verification Engineer, DDR Memory Subsystem

Role Posting Log in to save

The Design Verification Engineer - DDR Memory Subsystem joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the design, development, and manufacturing of computer chips, specifically the Azure Cobalt. You will own the verification of features within the Memory Controller IP or Subsystem by defining verification strategies and test plans. Daily responsibilities include developing UVM-based and Formal verification environments, running simulations, and applying random-stimulus and coverage-based techniques to identify bugs. You will also utilize generative AI solutions and Python for post-processing. Required technical knowledge includes Coherent Hub Interface (CHI), AMBA protocols, and JEDEC specifications. You will ensure high-quality hardware infrastructure by managing IP verification from initial definition through to final silicon signoff.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

See salary data

Skills

UVM System Verilog Formal Verification Python PCIe CXL AMBA CHI JEDEC Memory Controller IP Verification Generative AI Simulation SVTB

What you'll do

  • Own the verification of features within the Memory Controller IP or Subsystem.
  • Define verification strategies and test plans in coordination with partner teams.
  • Develop UVM-based and Formal verification environments to run and debug simulations.
  • Apply random-stimulus and coverage-based techniques to identify bugs and meet goals.
  • Innovate new methodologies and tools to improve overall verification efficiency.
  • Implement generative AI solutions to streamline and optimize verification work.
  • Coach and mentor team members in specific areas of technical expertise.

What we're looking for

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience.
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of technical engineering experience.
  • Ability to pass the Microsoft Cloud Background Check.
  • Must provide proof of citizenship, US residency, or other protected status for export control eligibility.
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field (preferred).
  • Master's Degree and 3+ years of experience, or Bachelor's Degree and 5+ years of experience (preferred).
  • Demonstrated understanding of CHI, AMBA protocols, JEDEC specifications, and memory controller or fabric interconnect designs (preferred).
  • Experience with UVM, SystemVerilog, formal verification, and Python scripting (preferred).

Related searches

More Design Verification Engineer jobs All jobs at Microsoft

More like this

Similar roles

ASIC Design Verification Engineer

Cisco

San Jose, CA 11 days ago $155,000–$222,600
System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification
5+ yrs exp
Save

Design Verification Engineer

Microsoft

27 days ago $102,100–$202,200
UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI Fabric Interconnects Generative AI Simulation Test Plans Coverage Signoff SVTB
2+ yrs exp Hybrid
Save

Design Verification Engineer

Microsoft

4 days ago $85,400–$168,100
UVM System Verilog Python Formal Verification PCIe CXL AXI AMBA CHI Generative AI IP Verification random-stimulus Protocol Bridges
2+ yrs exp Hybrid
Save

Design Verification Engineer

Microsoft

12 days ago $102,100–$202,200
SystemVerilog UVM C/C++ Python Ruby Perl Pre-silicon Verification Post-silicon Validation SOC Formal Verification PCIe DDR CXL AXI CHI Scripting Object-Oriented Programming Coverage-based Verification VIP SVTB
2+ yrs exp Hybrid
Save

Senior IP Design Verification Engineer

Microsoft

28 days ago $119,800–$234,700
UVM System Verilog Python CHI AMBA AXI PCIe CXL Generative AI IP Verification random-stimulus Simulation Test Bench Protocol Bridges Power Management Virtualization
5+ yrs exp Hybrid
Save

Principal Design Verification Engineer, Formal

Microsoft

4 days ago $142,800–$274,800
Formal Verification System Verilog UVM Python Fabric Interconnects CHI AMBA PCIe CXL Assertions Coverage-Driven Verification Simulation Root-Cause Analysis AI-assisted tools
8+ yrs exp Hybrid
Save