Next Gen High-Speed Memory and Cache Controller Design Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $101,400–$152,200 / yr
Posted: 20 days ago
Freshness: Confirmed live today
Closes: Apr 5, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $207k

This role $127k

$82k $283k

below market most similar roles pay here above market

This role pays less than 98% of similar roles. Most pay $177,250–$236,850 — the blue band above. At the midpoint, this role pays about $127k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Next Gen High-Speed Memory and Cache Controller Design Engineer

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Next Gen, High-Speed, Memory and Cache Controller Design Engineer The Next Generation, High-Speed, Memory and Cache Controller Design Team is seeking a Senior ASIC Design Engineer to develop high-speed HBM, LPDDR, and DDR memory controllers. You will define architecture, write RTL code, and manage the deployment of next-generation memory systems into products. Key responsibilities include developing design specifications, driving micro-architecture for logic design, and performing synthesis, timing closure, physical design support, gate level simulations, and power analysis. You must debug designs and provide integration support for the front end interfacing with CPUs, GPUs, and DSPs. Required expertise includes LPDDR and cache controller architectures, NoC based systems, x86 or ARM CPU/bus architectures, and memory transaction ordering to conform to ISA specifications. This role solves critical high-speed data processing and memory management problems.

Skills

ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA

What you'll do

Develop architecture and design specifications for next-generation high-speed memory systems.
Implement RTL coding for high-speed HBM, LPDDR, and DDR memory controllers.
Drive the micro-architecture for logic design portions of the memory controller.
Perform synthesis, timing closure, and physical design support for chip components.
Conduct gate level simulations and power analysis to ensure design quality.
Debug designs and provide technical support when integrated into the rest of the chip.
Contribute to the improvement of design methodologies to increase productivity and quality.

What we're looking for

Master's degree in Computer Engineering and/or Electrical Engineering.
Bachelor's degree in Science, Engineering, or a related field.
3+ years of experience (early-career professionals).
Experience with LPDDR memory and cache controller, NoC based architectures, and front end interfacing to CPU, DSP, and multimedia processors.
Exposure to HBM memory type designs.
Experience with on-chip tightly coupled SRAM and L3 cache controller architecture/design.
Experience with x86 or ARM CPU/bus architectures.
Experience with ordering memory transactions to conform to ISA architecture specifications.

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