below marketmost similar roles pay hereabove market
This role pays more than
65%
of similar roles. Most pay
$166,425–$241,750
— the blue band above.
At the midpoint, this role pays about
$218k
versus about
$204k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
Memory Designer
The Memory IP team is seeking a Memory Designer to develop and implement low-power, high-performance, and area-efficient embedded memory circuits and architectures for Snapdragon products. In this role, you will design custom digital circuits for high-speed and low-power SRAM designs, performing schematic capture, block simulation, margin verifications, and layout planning. You will collaborate with CAD teams for model generation and interact with SoC teams to define memory PPA targets. Required expertise includes CPU L1/L2 cache design, compiler SRAM/Register File architectures, and advanced custom circuit implementations. You must possess knowledge of semiconductor device fundamentals, variation-aware design in nanometer CMOS and FinFet technology nodes, and experience with tight pitch-matched memory layout designs. This position focuses on solving critical memory performance and power constraints within complex SoC environments.
Develop custom digital circuits for high-speed and low-power SRAM designs.
Perform schematic capture, simulation of major blocks, and margin verifications.
Manage layout planning and supervision for memory circuits.
Coordinate with the CAD team for full verification and model generation.
Collaborate with SoC teams to define memory PPA targets for CPU, GPU, and Modem components.
Implement low-power, high-performance, and area-efficient embedded memory architectures.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
2+ years of academic or professional experience designing embedded memories for SoC applications.
Knowledge of CPU L1/L2 cache design, compiler SRAM/Register File architectures, and advanced custom circuit implementations.
Knowledge of high-performance and low-power design features, techniques, and semiconductor device fundamentals.
Familiarity with variation-aware design in nanometer CMOS and FinFET technology nodes.
Experience with tight pitch-matched memory layout designs and understanding of physical implementation impact on circuit performance.