Memory Designer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$164,000–$246,000 / yr
Posted
72 days ago
Freshness
Confirmed live yesterday
Closes
Dec 29, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $205k
$139k most similar roles pay here $257k

This role pays more than 54% of similar roles. Most pay $168,200–$229,950 — the shaded band above. At the midpoint, this role pays about $205k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 621 open roles on FindRole.

Listed pay typically runs $147,900–$222,500 across 601 roles with salary data.

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At a glance

TL;DR · Memory Designer

As a Memory Designer on the Memory IP team, you will design and implement low-power, high-performance, and area-efficient embedded memory circuits and architectures for Snapdragon products. Your daily responsibilities include developing custom digital circuits for high-speed and low-power SRAM designs, performing schematic capture, simulating major blocks, conducting margin verifications, and overseeing layout planning. You will collaborate with CAD teams for full verification and model generation while interacting with SoC teams to define memory PPA targets. The role requires expertise in CPU L1/L2 cache design, compiler SRAM/Register File architectures, and advanced custom circuit implementations. You must possess knowledge of semiconductor device fundamentals, variation-aware design in nanometer CMOS and FinFET technology nodes, and tight pitch-matched memory layout designs to solve critical performance challenges within complex SoC environments including CPU, GPU, Modem, and Camera components.

What you'll do

  • Design custom digital circuits for high-speed and low-power SRAM designs.
  • Perform schematic capture and simulation of major memory blocks.
  • Conduct margin verifications for embedded memory circuits.
  • Oversee layout planning and supervision for memory components.
  • Coordinate with the CAD team for full verification and model generation.
  • Collaborate with SoC teams to define specific memory PPA targets.
  • Implement high-performance and low-power design features in advanced technology nodes.

What we're looking for

  • A Master's degree in Science or Engineering is required for entry-level candidates.
  • A PhD in Science or Engineering is also accepted as an alternative educational qualification.
  • Candidates with a Bachelor's degree must have 6+ years of ASIC design, verification, validation, or integration experience.
  • Candidates with a Master's degree must have 5+ years of ASIC design, verification, validation, or integration experience.
  • Candidates with a PhD must have 4+ years of ASIC design, verification, validation, or integration experience.
  • At least 2 years of academic or professional experience designing embedded memories for SoC applications is required.
  • Knowledge of CPU L1/L2 cache design and compiler SRAM/Register File architectures is required.
  • Experience with high-performance, low-power designs in advanced CMOS and FinFET technology nodes is required.

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