Browse tech roles

Formal Verification System Verilog UVM Python Fabric Interconnects CHI AMBA PCIe CXL Assertions Coverage-Driven Verification Simulation Root-Cause Analysis AI-assisted tools +9 more Show less

UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture ARM V7 Wireless Protocols Power Analysis RTL Design Debugging +12 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python RTL Digital Logic Design Constrained Random Testing Makefile Emulation Wireless Protocols Power Analysis SoC Design +10 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis +10 more Show less

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis +10 more Show less

UVM System Verilog Python Formal Verification PCIe CXL AXI AMBA CHI Generative AI IP Verification random-stimulus Protocol Bridges +8 more Show less

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP +10 more Show less

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP +10 more Show less

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP +10 more Show less

System Verilog UVM OVM C++ SystemC Perl RTL Verification ASIC Design Verification FPGA Emulators Coverage Assertions C Scripting +9 more Show less

System Verilog UVM ASIC Design Verification Python Perl TCL Shell Scripts Verilog Formal Verification Veloce HAPS Ethernet UCIE UAL SPI I2C SerDes D2D PHY ODSP +14 more Show less

SystemVerilog UVM Verilog ASIC Verification SystemVerilog Assertion Python Perl Matlab FPGA Palladium Constrained Random Testing Functional Coverage Machine Learning AI Bluetooth UWB WLAN Zigbee +13 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertion ASIC Verification Python Perl Matlab FPGA Palladium Constrained Random Testing Functional Coverage Machine Learning AI Wireless Protocols Bluetooth UWB WLAN Zigbee +14 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium ASIC Verification Constrained Random Testing Functional Coverage Machine Learning AI Bluetooth UWB WLAN Zigbee +14 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium ASIC Verification Constrained Random Testing Functional Coverage Machine Learning AI Bluetooth UWB WLAN Zigbee +14 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertion ASIC Verification Python Shell Perl FPGA Palladium Matlab Constrained Random Testing Functional Coverage Machine Learning AI Bluetooth UWB WLAN Zigbee +14 more Show less

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

FPGA VHDL ASIC CPLD UVM Xilinx Vivado Microchip Libero Intel Quartus Lattice Diamond DO-254 DOORS PCIe AXI SERDES DMA MIL-STD-1553 ARINC 429 ARINC 664 TSN Mentor Graphics HyperLynx Expedition Enterprise SoC +22 more Show less

UVM C C++ ASIC SoC Pre-Silicon Verification Post-Silicon Validation FPGA Simulation Emulation Coverage Closure Jasper Formal Verification Testbench Development Silicon Bring-up Firmware Computer Architecture +12 more Show less