Design Verification Engineer

Apple Inc

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Los Angeles, CA
Salary: $175,000–$308,500 / yr
Posted: 4 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $242k

$131k $327k

below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $242k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3544 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2734 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Design Verification Engineer

Role Posting Log in to save

JOB TITLE: Design Verification Engineer The Design Verification Engineer joins a hardware group to ensure bug-free first silicon for SoC and IP designs. This role involves all phases of pre-silicon verification, including establishing DV methodology, developing test plans based on micro-architecture, and building scalable, portable verification environments. Day-to-day tasks include developing stimulus, checkers, assertions, and trackers, as well as executing design bring-up, regression enabling, and debugging test failures. The engineer must track progress using metrics like bugs and coverage. Key technical requirements include deep knowledge of SystemVerilog, UVM, and OOP, along with proficiency in scripting languages like Python, Perl, or TCL. Candidates should also have experience with simulators, waveform viewers, and gate level simulations. Additionally, the role utilizes LLMs for efficient execution and may involve power-aware UPF methodologies.

What does a Design Verification Engineer earn in California?

Median $199724 from 59 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP

What you'll do

Create comprehensive test plans based on design specifications and micro-architecture.
Develop scalable and portable verification environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs identified during regression cycles.
Track and report verification progress using metrics such as bug counts and coverage.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform pre-silicon verification to ensure bug-free first silicon for SoC and IP designs.

What we're looking for

BS degree in a technical subject area.
Minimum 10 years of proven experience or equivalent.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, and coverage collection (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).