below marketmost similar roles pay hereabove market
This role pays less than
61%
of similar roles. Most pay
$168,500–$230,087
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The Design Verification Engineer joins the wireless silicon development team to support the wireless SOC organization. This role focuses on highly energy efficient designs and new technologies. The engineer will design and implement C tests for wireless SOC verification and power analysis while collaborating with architecture and RTL power designers. Key responsibilities include defining power vector tests, developing test plans and environments, and performing cross-functional reviews. Required technical skills include C, C++, assembly, Verilog, and SystemVerilog, along with knowledge of C compilation flows, makefiles, and reusable verification frameworks. The role requires expertise in constrained random testing, debugging, and digital logic design. Candidates should understand chip architecture, ARM V7 or V8 architectures, and wireless protocols to solve complex verification problems for functional products.
What does a Design Verification Engineer earn in California?
Median $199500 from 57 postings across 7 companies.
SystemVerilog
UVM
Python
Perl
C++
Assembly
Digital Simulation
Constrained Random Verification
Functional Coverage
Code Coverage
Assertion Methodology
Computer Architecture
Digital Design
PCI Express
DisplayPort
MIPI
Data Structures and Algorithms
System Verilog
UVM
C
C++
Python
Perl
EDA Tools
Digital Design
Computer Architecture
Constrained Random Verification
Functional Coverage
ASIC Design Flow
High-speed Interface Protocols
Regression Analysis
Verification IP
UVM
SystemVerilog
Verilog
C
C++
Assembly
Python
RTL
Digital Logic Design
Constrained Random Testing
Makefile
Emulation
Wireless Protocols
Power Analysis
SoC Design