below marketmost similar roles pay hereabove market
This role pays less than
99%
of similar roles. Most pay
$169,625–$230,087
— the blue band above.
At the midpoint, this role pays about
$127k
versus about
$200k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
694 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 651 roles with salary data.
JOB TITLE: Design Verification Engineer
The Design Verification Engineer joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the design, development, manufacturing, and packaging of custom computer chips, specifically the Azure Cobalt. You will own the verification of custom IP blocks or subsystem integrations by defining verification strategies and test plans. Day-to-day responsibilities include developing UVM-based or Formal verification environments, running simulations, and applying random-stimulus and coverage-based techniques to identify bugs. You will utilize System Verilog, Python, and generative AI solutions to improve verification efficiency. The role requires technical knowledge of fabric interconnects, coherency, CHI, AXI, AMBA, virtualization, security, interrupts, PCIe, and CXL to ensure high-quality hardware manufacturing and infrastructure optimization for cloud services.
What does a Design Verification Engineer earn?
Median $189224 from 84 postings across 10 companies.
Own the verification of specific features or subsystems within custom IP blocks.
Define verification strategies and test plans by interacting with partner design teams.
Develop UVM-based or Formal verification environments to run and debug simulations.
Apply random-stimulus and coverage-based techniques to identify bugs and meet goals.
Innovate new methodologies and tools to improve overall verification efficiency.
Implement generative AI solutions to streamline and optimize verification work.
Coach and mentor team members in specific areas of technical expertise.
What we're looking for
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements.
Must provide proof of citizenship or U.S. permanent residency for export-controlled information access.
Master's Degree in a related field OR a Bachelor's Degree with 2+ years of technical engineering experience (preferred).
One year of pre-silicon subsystem or IP/block level verification experience (preferred).
Demonstrated understanding of complex IP/blocks such as fabric interconnects, coherency, CHI, AXI, AMBA, virtualization, security, interrupts, PCIe, or CXL (preferred).
Experience creating and integrating test benches using UVM, System Verilog Test Bench, and Python (preferred).
Experience applying generative AI to day-to-day tasks (preferred).
UVM
System Verilog
Python
CHI
AMBA
AXI
PCIe
CXL
Generative AI
IP Verification
random-stimulus
Simulation
Test Bench
Protocol Bridges
Power Management
Virtualization