Design Verification Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live yesterday
Closes
Apr 18, 2027
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $200k
$141k $242k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $169,625–$230,087.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the ASIC Product Division within a high performance design team focused on state-of-the-art subsystem development. The role involves developing verification environments using modern techniques to meet specific customer requirements. Key responsibilities include designing verification components like UVM agents and behavioral models, implementing coverage and assertions using System Verilog, and developing random and directed test cases against specifications. The engineer will analyze and debug simulation failures while evaluating coverage results. Required technical skills include fluency in RTL verification methodologies, System Verilog, UVM, OVM, C/C++, and Perl scripting. The work involves verifying designs at both system and block levels, specifically addressing complex verification trade-off scenarios for SoC and IP development programs involving CPU, DDR, Bus, Network, or DSP designs.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

System Verilog UVM OVM C++ SystemC Perl RTL Verification ASIC Design Verification FPGA Emulators Coverage Assertions C Scripting

What you'll do

  • Develop verification environments using System Verilog and UVM.
  • Design verification components including UVM agents and behavioral models.
  • Implement coverage and assertions using System Verilog.
  • Develop random and directed test cases against specifications.
  • Analyze and debug simulation failures and coverage results.
  • Resolve complex verification trade-off scenarios.
  • Perform system and sub-block level verification.

What we're looking for

  • Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ years of relevant industry work experience.
  • Experience in verifying designs at system level and block level.
  • Fluent knowledge of RTL verification methodologies including System Verilog.
  • Strong experience in ASIC design verification flows and DV methodologies.
  • Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.
  • Strong and independent design debugging capability.
  • Must have legal authorization to work in the US.
  • Experience with hardware design and debug, C++/SystemC, and other programming languages (preferred).

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