PHY Design Verification Engineer

Apple Inc

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Work type
On-site
Location
San Francisco, CA
Salary
$129,300–$225,300 / yr
Posted
6 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $199k
This role $177k
$117k $245k
below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $169,625–$229,100 — the blue band above. At the midpoint, this role pays about $177k versus about $199k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · PHY Design Verification Engineer

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JOB TITLE: PHY Design Verification Engineer The PHY Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of wireless PHY and its interfaces within the wireless communication SoC. You will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven verification. Key responsibilities include creating verification plans from specifications, building block-level testbenches with reference models, and executing directed and constrained random tests. You will manage bug tracking, analyze coverage models, and utilize machine learning and AI technologies to identify design issues. Required skills include Verilog, SystemVerilog, UVM, and SystemVerilog Assertion. The role involves supporting PHY subsystem validation using Palladium and FPGA while addressing technical challenges in wireless protocols like Bluetooth, UWB, WLAN, or Zigbee.

Skills

SystemVerilog UVM Verilog SystemVerilog Assertion ASIC Verification Python Perl Matlab FPGA Palladium Constrained Random Testing Functional Coverage Machine Learning AI Wireless Protocols Bluetooth UWB WLAN Zigbee

What you'll do

  • Create verification plans from specifications and refine them to achieve coverage targets.
  • Build reusable block and subsystem level test benches using a reference model.
  • Develop and execute directed and constrained random tests to identify design flaws.
  • Debug failures, manage bug tracking, and work with designers to drive issue closure.
  • Create and analyze coverage models while adding test cases to increase coverage.
  • Use machine learning and AI technologies to identify design and test bench issues.
  • Support PHY subsystem validation using Palladium and FPGA platforms.
  • Improve DV methodology and flows in coordination with team members.

What we're looking for

  • Minimum requirement of a bachelor's degree.
  • Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
  • Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
  • MSEE with 2+ years of verification experience of wireless/wired communication block/subsystem (preferred).
  • Experience using Matlab/C reference models and bit-accurate verification (preferred).
  • Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
  • Proficient in shell, Python, and Perl scripting (preferred).
  • Experience using AI technologies in data mining/analysis or Palladium/FPGA validation (preferred).

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