Principal Design Verification Engineer, Formal

Microsoft

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$142,800–$274,800 / yr
Posted
2 days ago
Freshness
Confirmed live today
Closes
Apr 3, 2027

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 56% of similar roles. Most pay $175,400–$233,050 — the shaded band above. At the midpoint, this role pays about $209k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 599 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 564 roles with salary data.

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At a glance

TL;DR · Principal Design Verification Engineer, Formal

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The Principal Design Verification Engineer - Formal will join the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role involves leading the formal verification of Fabric Interconnect architectures, IPs, subsystems, and reusable components from planning through signoff. The engineer will develop formal verification environments, assertions, abstraction models, and checkers while driving root-cause analysis for complex design issues. Key responsibilities include improving productivity through automation and AI-assisted solutions and mentoring other engineers. Required technical skills include expertise in pre-silicon subsystem or IP formal verification, System Verilog, UVM, and Python. The role addresses the technical challenge of ensuring high-quality, high-volume hardware manufacturing for cloud infrastructure, specifically focusing on complex protocols like CHI, AMBA, PCIe, CXL, and memory subsystems.

What does a Design Verification Engineer earn?

Median $199612 from 78 postings across 10 companies.

See salary data

Skills

Formal Verification System Verilog UVM Python Fabric Interconnects CHI AMBA PCIe CXL Assertions Coverage-Driven Verification Simulation Root-Cause Analysis AI-assisted tools

What you'll do

  • Lead Formal verification of Fabric Interconnect architectures, IPs, subsystems, and reusable components from planning through signoff.
  • Define Formal verification strategies, methodologies, test plans, and signoff criteria in partnership with architecture and design teams.
  • Develop and enhance Formal verification environments, assertions, abstraction models, checkers, and reusable collateral.
  • Drive root-cause analysis and closure of complex design and verification issues using Formal analysis, simulation, and debug.
  • Improve verification productivity through automation, new methodologies, and AI-assisted solutions.
  • Coach and mentor engineers on Formal verification methodologies and best practices.

What we're looking for

  • Require a Doctorate with 3+ years of experience, a Master's with 6+ years, or a Bachelor's with 8+ years in a related engineering field.
  • Require the ability to pass a Microsoft Cloud Background Check every two years.
  • Require proof of citizenship, US residency, or other protected status to access export-controlled information.
  • Require ability to meet government security screening requirements.
  • Require 1+ year of experience leading projects from beginning-to-end (preferred).
  • Require 5+ years of pre-silicon subsystem or IP Formal verification experience (preferred).
  • Require expertise in Formal verification methodologies for complex IPs, SoCs, or reusable library components (preferred).
  • Require expertise in Fabric Interconnects, coherency, CHI, AMBA, PCIe, CXL, or memory subsystems (preferred).

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