Design Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$175,000–$308,500 / yr
Posted
4 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $242k
$131k $327k
below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $242k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the wireless silicon development team to support the wireless SOC organization. This role focuses on highly energy efficient designs and new technologies for wireless silicon. The engineer will design and implement C tests for verification and power analysis, collaborating with architecture and RTL power designers to define power vector tests and verify functionality correctness. Key responsibilities include developing test plans and environments in C or UVM, creating complex power vector tests in C or assembly, and performing cross-functional reviews. Required skills include C/C++, assembly, Verilog, SystemVerilog, and makefiles. The role requires expertise in constrained random testing, debugging, and reusable verification frameworks. Candidates should understand digital logic design, chip architecture, and wireless protocols to solve complex hardware verification problems.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis

What you'll do

  • Define power vector tests with architecture and RTL power designers to verify SoC functionality.
  • Develop comprehensive test plans and test environments using C or UVM.
  • Create complex power vector tests for wireless protocol designs in C or assembly.
  • Execute test plans and perform technical reviews with cross-functional teams.
  • Perform debugging and problem-solving for constrained random testing and reusable verification frameworks.
  • Port simulation tests to emulation environments for hardware verification.
  • Develop system-level tests using Python or other scripting languages.

What we're looking for

  • BS degree and a minimum of 10 years of relevant industry experience.
  • Experience with C/C++/assembly programming and Verilog/SystemVerilog.
  • Understanding of C compilation flow and makefile.
  • Solid verification skills in problem solving, constrained random testing, and debugging.
  • Solid understanding of reusable verification frameworks.
  • Knowledge of digital logic design, chip architecture, and microarchitecture.
  • Experience in setting UVM/System TB with embedded C tests (preferred).

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