Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $184,700–$324,800 / yr
Posted: 4 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $255k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3544 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2734 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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JOB TITLE: Design Verification Engineer As a Design Verification Engineer, you will join a hardware group to enable the production of fully functional first silicon for IP designs. You will be responsible for all phases of pre-silicon verification, including establishing DV methodology, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves developing stimulus, checkers, assertions, and trackers while performing test-writing, debugging, and coverage analysis for RTL freeze and tape-out. You will utilize SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL to stress designs. Additionally, you will leverage LLMs to improve execution efficiency. The role focuses on ensuring bug-free SoC and IP components by managing regressions, tracking metrics, and performing power-aware verification using UPF methodologies.

What does a Design Verification Engineer earn in California?

Median $199724 from 59 postings across 7 companies.

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Skills

SystemVerilog UVM Python Perl TCL LLM UPF PCIe USB DDR Formal Verification Gate Level Simulation Simulators Waveform Viewers OOP

What you'll do

Create comprehensive test plans based on design specifications and micro-architecture.
Develop scalable and portable verification environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs identified during regression cycles.
Track and report verification progress using bugs and coverage metrics.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform pre-silicon verification for RTL freeze and tape-out sign-off.

What we're looking for

BS degree in a technical subject area.
Minimum 10 years of relevant industry experience.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, and coverage collection (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of scripting languages such as Python, Perl, or TCL (preferred).

Design Verification Engineer

Amd

Santa Clara, CA 146 days ago $166,400–$249,600

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification

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