Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,700–$214,300 / yr
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $168k

$110k $246k

below market most similar roles pay here above market

This role pays less than 75% of similar roles. Most pay $169,625–$230,087 — the blue band above. At the midpoint, this role pays about $168k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the wireless silicon development team to support the design of wireless SoCs with a focus on energy efficiency and new technologies. This role involves collaborating with architecture and RTL power designers to define power vector tests and verify functionality correctness. Key responsibilities include developing test plans and environments, creating complex power vector tests for wireless protocol designs, and performing cross-functional reviews. The candidate must utilize C, C++, assembly, Verilog, and SystemVerilog, while demonstrating proficiency in UVM, makefiles, and constrained random testing. Technical requirements include knowledge of digital logic design, chip architecture, and ARM V7 or V8 architectures. The work addresses the technical challenge of ensuring functional correctness and power analysis for complex wireless silicon products.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

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Skills

UVM SystemVerilog Verilog C C++ Assembly Python RTL Digital Logic Design Constrained Random Testing Makefile Emulation Wireless Protocols Power Analysis SoC Design

What you'll do

Develop test plans and test environments using C or UVM.
Design and implement complex power vector tests for wireless protocol designs in C or assembly.
Define power vector tests and verify functionality correctness of the Wireless SoC design.
Prepare and execute test plans while performing reviews with cross-functional teams.
Port simulation tests to emulation environments.
Perform debugging and problem-solving for constrained random testing.
Develop system-level tests using Python or other scripting languages.

What we're looking for

Minimum requirement of a bachelor's degree.
Experience with C/C++/assembly programming and Verilog/SystemVerilog.
Understand C compilation flow and makefile.
Solid verification skills in problem solving, constrained random testing, and debugging.
Solid understanding of reusable verification framework.
Knowledge of digital logic design, chip architecture, and microarchitecture.
Experience in setting UVM/System TB with embedded C tests (preferred).

Design Verification Engineer

Apple Inc

Sunnyvale, CA 4 days ago $129,300–$225,300

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture ARM V7 Wireless Protocols Power Analysis RTL Design Debugging

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