below marketmost similar roles pay hereabove market
This role pays less than
63%
of similar roles. Most pay
$176,493–$227,500
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$202k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
694 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 651 roles with salary data.
The Sr. Design Verification Engineer - Fabric Interconnect Performance joins the Verification & Validation team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on the performance verification of Fabric Interconnect subsystems, specifically addressing traffic management, QoS, latency, bandwidth, and congestion scenarios for cloud hardware. The engineer will develop performance analytics, monitors, scoreboards, and visualization tools while building and enhancing UVM and Formal verification environments. Key responsibilities include driving bug discovery through simulation, assertions, and coverage, as well as improving productivity via automation and AI-driven solutions. Required technical skills include experience with complex IPs, SoCs, and protocols like CHI, AMBA, PCIe, and CXL. The role requires proficiency in Python for scripting and data analysis to optimize high-volume cloud infrastructure components.
What does a Design Verification Engineer earn?
Median $189224 from 84 postings across 10 companies.
Own performance verification of Fabric Interconnect subsystems including traffic management, QoS, latency, bandwidth, and congestion.
Define verification strategies, test plans, and signoff criteria in partnership with architecture and design teams.
Develop performance analytics, monitors, scoreboards, heat maps, and visualization tools to identify design bottlenecks.
Develop and enhance UVM and Formal verification environments, infrastructure, and reusable collateral.
Drive bug discovery and root-cause analysis using simulation, formal analysis, assertions, coverage, and debug.
Improve verification productivity through automation, methodologies, and AI-driven solutions.
Coach and mentor engineers in verification methodologies and best practices.
What we're looking for
Obtain a Doctorate in a related field with 1+ years of experience, a Master's with 4+ years, or a Bachelor's with 5+ years of experience.
Possess equivalent technical engineering experience to the degree and years of experience requirements.
Ability to pass the Microsoft Cloud Background Check every two years.
Provide proof of citizenship, US residency, or other protected status for export control eligibility.
Experience with performance verification of complex IPs, subsystems, or SoCs, including latency, bandwidth, QoS, and congestion management (preferred).
Demonstrated understanding of fabric interconnects, coherency, CHI, AMBA, PCIe, CXL, protocol bridges, or memory subsystems (preferred).