below marketmost similar roles pay hereabove market
This role pays less than
75%
of similar roles. Most pay
$173,281–$229,100
— the blue band above.
At the midpoint, this role pays about
$168k
versus about
$201k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
JOB TITLE: PHY Design Verification Engineer
The PHY Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of the wireless PHY and its interfaces within the wireless communication SoC. The engineer will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven verification. Key responsibilities include creating verification plans from specifications, building block-level testbenches with reference models, executing directed and constrained random tests, and managing bug tracking. The role requires advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion, along with experience in ASIC verification flows. Candidates should be proficient in shell, Python, and Perl scripting. The work involves solving complex wireless communication problems for protocols like Bluetooth, UWB, WLAN, and Zigbee using Palladium, FPGA, and AI technologies.
Create verification plans from specifications and refine them to achieve coverage targets.
Build reusable block and subsystem level test benches using best-in-class DV methodology.
Develop and execute directed and constrained random tests to identify and debug failures.
Create and analyze block/subsystem-level coverage models to increase test coverage.
Use machine learning and AI technologies to identify design and test bench issues.
Support PHY subsystem validation using Palladium and FPGA platforms.
Improve DV methodology and flows in coordination with team members.
What we're looking for
Minimum requirement of a bachelor's degree.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
MSEE with 2+ years of verification experience of wireless/wired communication block/subsystem (preferred).
Experience using Matlab/C reference models and bit-accurate verification (preferred).
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
Proficient in shell, Python, and Perl scripting (preferred).
Experience using AI technologies in data mining/analysis and Palladium/FPGA validation (preferred).