PHY Design Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$175,000–$308,500 / yr
Posted
6 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $242k
$131k $327k
below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $169,625–$229,100 — the blue band above. At the midpoint, this role pays about $242k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · PHY Design Verification Engineer

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JOB TITLE: PHY Design Verification Engineer The PHY Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of the wireless PHY and its interfaces within the wireless communication SoC. This role involves collaborating with DV methodologists, designers, and communication systems engineers to develop reusable test benches and verification environments using metric-driven methodologies. Key responsibilities include creating verification plans from specifications, building block-level test benches with reference models, executing directed and constrained random tests, and managing bug tracking. The position requires proficiency in Verilog, SystemVerilog, UVM, and SystemVerilog Assertion, along with experience in ASIC verification flows, shell, Python, and Perl scripting. Candidates may use Matlab, Palladium, FPGA, and AI technologies to ensure high design quality for wireless protocols like Bluetooth, UWB, WLAN, or Zigbee.

Skills

SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium ASIC Verification Constrained Random Testing Functional Coverage Machine Learning AI Bluetooth UWB WLAN Zigbee

What you'll do

  • Create verification plans from specifications and refine them to achieve specific coverage targets.
  • Build reusable block and subsystem level test benches using a reference model and best-in-class DV methodology.
  • Develop and execute directed and constrained random tests to identify and debug design failures.
  • Manage bug tracking and work directly with designers to drive the closure of identified issues.
  • Create and analyze block/subsystem-level coverage models and add test cases to increase coverage.
  • Use machine learning and AI technologies to identify design issues and ensure verification quality.
  • Support PHY subsystem validation using Palladium and FPGA platforms.
  • Improve overall DV methodology and flow through continuous collaboration with team members.

What we're looking for

  • BS degree and a minimum of 10 years of relevant industry experience.
  • Verification experience of wireless or wired communication blocks and subsystems.
  • Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
  • Excellent knowledge of ASIC verification flows, including test bench development, constrained random testing, and coverage.
  • Experience using Matlab/C reference models and bit-accurate verification (preferred).
  • Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
  • Proficiency in shell, Python, and Perl scripting (preferred).
  • Experience using AI technologies for data mining/analysis or Palladium/FPGA validation (preferred).

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