Design Verification Technical Leader

Cisco

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Carlsbad, CAAllentown, PA
Salary: $192,400–$275,800 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Closes: Nov 24, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $234k

$135k $291k

below market most similar roles pay here above market

This role pays more than 75% of similar roles. Most pay $177,250–$233,537 — the blue band above. At the midpoint, this role pays about $234k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Design Verification Technical Leader

Role Posting Log in to save

The Design Verification Technical Leader joins the Silicon One Optics group to lead the verification of high-speed silicon photonics driver ICs. This role involves defining verification methodologies and standards across multiple projects while coordinating activities across various sites. You will lead verification at the block and chip levels for high-speed IPs, including SerDes XSR/PAM4, D2D IP, and integrated drivers. Key responsibilities include reviewing specifications, influencing architecture for testability, mentoring engineers, and debugging complex silicon issues during bring-up. Required skills include SystemVerilog, UVM, and scripting in Python, Perl, TCL, or Shell Scripts. You will work on hyper-scalable optical transceivers and modules for 800G and 1.6T workloads, solving technical challenges in high-speed networking for next-generation data centers and AI/ML infrastructure.

Skills

System Verilog UVM ASIC Design Verification Python Perl TCL Shell Scripts Verilog Formal Verification Veloce HAPS Ethernet UCIE UAL SPI I2C SerDes D2D PHY ODSP

What you'll do

Define and lead verification methodology and standards across multiple projects and sites.
Lead block and chip level verification for high-speed silicon photonics driver ICs.
Review specifications and participate in design reviews to influence architecture for testability.
Mentor and coach verification engineers to improve technical skills and execution.
Debug complex silicon and system-level issues during the bring-up phases.
Support post-silicon bring-up and optimize integration and performance.
Develop scalable, reusable, and coverage-driven verification environments using UVM.

What we're looking for

Bachelor’s degree in Electrical or Computer Engineering with 8+ years of ASIC Design Verification experience.
Master’s degree in Electrical Engineering or Computer Engineering with 6+ years of ASIC Design experience.
PhD in Electrical Engineering or Computer Engineering with 3 years of ASIC Design Verification experience.
Experience in System Verilog, UVM, and verification methodologies.
Experience owning and delivering verification for large-scale SoCs or subsystems.
Experience leading verification teams or projects.
Experience in scripting and automation using Python, Perl, TCL, or Shell Scripts.
Strong experience with UVM for developing scalable, reusable, and coverage-driven verification environments (preferred).

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