below marketmost similar roles pay hereabove market
This role pays more than
85%
of similar roles. Most pay
$168,500–$229,100
— the blue band above.
At the midpoint, this role pays about
$242k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The Design Verification Engineer joins a hardware group to ensure bug-free first silicon for SoC and IP designs. This role involves all phases of pre-silicon verification, including establishing DV methodology, developing test plans based on micro-architecture, and building scalable, portable verification environments. The engineer will develop stimulus, checkers, assertions, and trackers while executing design bring-up, regression enabling, and debugging test failures. Key responsibilities include tracking progress through bugs and coverage metrics to achieve sign-off for RTL freeze and tape-out. Required technical skills include SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL. The role also utilizes LLMs for efficient execution and quality. Candidates should possess experience with simulators, waveform viewers, coverage collection, gate level simulations, and power-aware UPF methodologies.
What does a Design Verification Engineer earn in California?
Median $199500 from 57 postings across 7 companies.
Create comprehensive test plans based on design specifications and micro-architecture.
Develop scalable and portable verification environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs identified during regression cycles.
Track and report verification progress using bugs and coverage metrics.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Manage all phases of pre-silicon verification to ensure bug-free first silicon.
What we're looking for
BS degree in a technical subject area with minimum 10 years of proven experience or equivalent.
Deep knowledge of OOP, SystemVerilog, and UVM (preferred).
Deep knowledge in developing scalable and portable test-benches (preferred).
Strong experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL (preferred).
Experience with serial protocols like PCIe or USB, parallel protocols like DDR, formal verification, or emulation technologies (preferred).
SystemVerilog
UVM
Python
Perl
C++
Assembly
Digital Simulation
Constrained Random Verification
Functional Coverage
Code Coverage
Assertion Methodology
Computer Architecture
Digital Design
PCI Express
DisplayPort
MIPI
Data Structures and Algorithms