Senior Design Verification Engineer

Microsoft

Confirmed live yesterday Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: —
Salary: $119,800–$234,700 / yr
Posted: 10 days ago
Freshness: Confirmed live yesterday
Closes: Apr 14, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k

This role $177k

$106k $248k

below market most similar roles pay here above market

This role pays less than 58% of similar roles. Most pay $168,500–$222,125 — the blue band above. At the midpoint, this role pays about $177k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 711 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 668 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Senior Design Verification Engineer

Role Posting Log in to save

The Senior Design Verification Engineer joins the Shared and Custom IP & Silicon team within the Compute Silicon & Manufacturing Engineering organization. This role focuses on block and sub-system level verification for custom Intellectual Property components used in cloud hardware. The engineer will define pre-silicon verification strategies for simulation, emulation, and FPGA testing, while also managing post-silicon validation and silicon bring-up activities. Key responsibilities include developing test plans, executing end-to-end verification, and ensuring coverage closure. Required technical skills include UVM based verification methodology, C and C++ programming for testbench development, and formal verification using Jasper. The role addresses the technical challenge of delivering high-quality, high-volume hardware infrastructure for cloud services by ensuring the reliability and performance of complex Application Specific Integrated Circuits and System on Chips.

What does a Design Verification Engineer earn?

Median $190899 from 86 postings across 10 companies.

See salary data

Skills

UVM C C++ ASIC SoC Pre-Silicon Verification Post-Silicon Validation FPGA Simulation Emulation Coverage Closure Jasper Formal Verification Testbench Development Silicon Bring-up Firmware Computer Architecture

What you'll do

Define pre-silicon verification strategies and develop comprehensive test plans for custom IP components.
Execute end-to-end verification plans at the block, sub-system, and system levels.
Develop and manage UVM-based verification methodologies to achieve coverage closure.
Write C-based testbenches and test infrastructure for hardware verification.
Perform silicon bring-up activities and conduct post-silicon validation testing.
Provide technical leadership and mentorship to the verification team.
Implement AI-based tools and agents to improve verification execution efficiency.

What we're looking for

Obtain a Doctorate with 1+ years of experience, a Master's with 4+ years, or a Bachelor's with 5+ years in a relevant engineering field.
Ability to pass the Microsoft Cloud Background Check and meet export control regulations.
Provide proof of U.S. citizenship, permanent residency, or other protected status for export-controlled information access.
Expertise in UVM based verification methodology including coverage closure.
Basic C, C++ programming understanding to develop C based testbenches.
Experience in silicon validation test planning, silicon bring-up, and validation activities.
7+ years of experience in design verification, developing test plans, and debugging for multiple IPs, sub-systems, or SoCs (preferred).
3+ years of experience in silicon bring-up and post-silicon validation for complex ASICs or SoCs (preferred).

Save