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Active Keyword: Design Verification Engineer Remove filter Location: San Jose Remove filter Clear all

12 of up to 20 (filtered)

ASIC Design Verification Engineer

Cisco

San Jose, CA 3 days ago $167,700–$245,200
Actively hiring Confirmed live 2 days ago Posted this week High trust Competitive pay
System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug
7+ yrs exp
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Senior Staff Design Verification Engineer

Amd

San Jose, CA 7 days ago $200,000–$300,000
Actively hiring Confirmed live 2 days ago Posted this week High trust Above market
DFT Verilog SystemVerilog ATPG Scan MBIST LBIST Boundary Scan UVM OVM RTL Design Static Timing Analysis Python Tcl Perl Shell Synopsys DFT Compiler TestMAX PrimeTime VCS Cadence tool s FPGA
Hybrid
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Senior Staff Engineer, GPU Design Verification (Subsystems)

Samsung Electronics

Remote (San Jose, CA) 15 days ago $180,200–$297,200
Actively hiring Confirmed live yesterday High trust Above market
SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects
10+ yrs exp Remote
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Masters Hardware Design Verification Engineering Co-op/Intern

Amd

San Jose, CA +1 22 days ago $83,200–$124,800
Actively hiring Confirmed live 2 days ago Trusted Below market
Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Digital Systems Computer Organization Hardware Design Simulation Debugging Oscilloscopes
Hybrid
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Undergrad Hardware Design Verification Engineering Co-op/Intern

Amd

San Jose, CA +1 22 days ago $64,064–$96,096
Actively hiring Confirmed live yesterday Trusted Below market
Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Logic Design Simulation Debugging Oscilloscopes Logic Analyzers
Hybrid
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Design Verification Engineer

Broadcom

Broomfield, CO +4 38 days ago $143,800–$230,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
SystemVerilog UVM SVA RTL Gate-level Netlists Python Perl Tcl Git FPGA Emulation Synopsys Cadence Mentor Co-simulation iJTAG Tessent DesignSync
10+ yrs exp
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ASIC Design Verification Engineer, Technical Leader

Cisco

San Jose, CA 38 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago High trust Above market
System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation
8+ yrs exp
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ASIC Design Verification Engineering Leader

Cisco

Remote (San Jose, CA) 38 days ago $214,100–$309,800
Actively hiring Confirmed live yesterday High trust Above market
SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4
10+ yrs exp Remote
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ASIC Design Verification Engineer

Cisco

Remote (San Jose, CA) 53 days ago $165,000–$241,400
Actively hiring Confirmed live yesterday Low trust Competitive pay
System Verilog UVM ASIC Design C C++ Python Perl Linux Formal Verification Networking Post-silicon Lab Bring-up
7+ yrs exp Remote
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Design Verification Engineer

Broadcom

San Jose, CA 84 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday Trusted Competitive pay
System Verilog UVM OVM C C++ Perl SystemC RTL Verification ASIC Design FPGA Emulators DSP Scripting
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Design Verification Engineer

Broadcom

San Jose, CA 84 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday Trusted Competitive pay
System Verilog UVM OVM C C++ SystemC Perl RTL Verification ASIC Design FPGA Emulators DSP Scripting
10+ yrs exp
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Senior Staff Engineer, Design Verification

Samsung Semiconductor

San Jose, CA 171 days ago $189,000–$301,000
Actively hiring Confirmed live yesterday High trust Above market
UVM System Verilog C++ Python Perl RTL SoC FPGA Emulation AI Accelerators Computer Architecture Interconnect Networks Simulation
10+ yrs exp
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