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Active Keyword: Design Verification Engineer Remove filter Location: San Jose Remove filter Clear all

20 of up to 20 (filtered)

Design Verification Engineer

Broadcom

San Jose, CA 5 days ago
Actively hiring Confirmed live yesterday Posted this week High trust
System Verilog UVM OVM C++ SystemC Perl RTL Verification ASIC Design Verification FPGA Emulators Coverage Assertions C Scripting
10+ yrs exp
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Senior ASIC Design Verification Engineer

Cisco

San Jose, CA 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP
7+ yrs exp
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ASIC Design Verification Engineer

Cisco

San Jose, CA 11 days ago $155,000–$222,600
Actively hiring Confirmed live today Trusted Competitive pay
System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification
5+ yrs exp
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ASIC Design Verification Engineer

Cisco

San Jose, CA 13 days ago $155,000–$222,600
Actively hiring Confirmed live today High trust Competitive pay
System Verilog UVM Python Perl ASIC Design Verification Gate Level Simulation Veloce Palladium Zebu HAPS VC Formal IEV P4 PCIe CXL Ethernet RDMA DDR TCP
5+ yrs exp
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GPU Design Verification Engineer

Samsung Electronics

San Jose, CA +1 15 days ago $180,200–$297,200
Actively hiring Confirmed live today Trusted Above market
GPU Design Verification C++ Python SystemVerilog Verilog UVM Graphics Pipeline 3D Graphics Shaders Graphics APIs Formal Verification GPU Architecture
10+ yrs exp
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Senior Staff Engineer, GPU Design Verification (Subsystems)

Samsung Electronics

San Jose, CA +1 15 days ago $180,200–$297,200
Actively hiring Confirmed live today High trust Above market
SystemVerilog UVM C++ Python Perl GPU Design Verification Constrained-Random Testing Coverage-Driven Verification RTL Computer Architecture Hardware Modeling Emulation Performance Profiling Formal Verification
10+ yrs exp
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Design Verification Engineer

Broadcom

San Jose, CA 26 days ago
Actively hiring Confirmed live today High trust
System Verilog UVM OVM C++ SystemC Perl RTL Verification ASIC Design Verification FPGA Emulators Coverage Assertions CPU DDR DSP
8+ yrs exp
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Lead Design Verification Engineer, Memory Controller

Amd

San Jose, CA 35 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal Network-on-Chip Regression Management
8+ yrs exp
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Digital Design Verification Engineer

Broadcom

San Jose, CA +1 43 days ago $101,000–$162,000
Actively hiring Confirmed live yesterday High trust Below market
UVM Design Verification SoC Integration Design Debug Timing Closure Physical Design test bench setup
5+ yrs exp
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Senior Staff Design Verification Engineer

Amd

San Jose, CA 53 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog UVM DFT RTL Design Python Tcl Perl Shell Static Timing Analysis ASIC SoC FPGA Synopsys Cadence PCIe SerDes HBM Synthesis Place-and-Route
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Design Verification Engineer, Coherent Interconnect

Samsung Electronics

Austin, TX +1 67 days ago $151,000–$251,800
Actively hiring Confirmed live today High trust Competitive pay
SystemVerilog UVM Unix Perl Git UPF Gate-level Simulation Formal Verification LPDDR SoC
10+ yrs exp
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Masters Hardware Design Verification Engineering Co-op/Intern

Amd

San Jose, CA +1 67 days ago $83,200–$124,800
Actively hiring Confirmed live today Trusted Below market
system Verilog Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows Hardware Design Verification Digital Systems Computer Organization Logic Design HDL Oscilloscopes Logic Analyzers
Hybrid
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Hardware Design Verification Engineering Co-op/Intern

Amd

San Jose, CA +1 67 days ago $64,064–$96,096
Actively hiring Confirmed live today Trusted Below market
Verilog system Verilog Python C++ Perl UVM C Shell MySQL PHP Linux Unix Windows Hardware Design Verification Digital Systems Logic Design HDL Oscilloscopes Logic Analyzers
Hybrid
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Design Verification Engineer

Broadcom

Broomfield, CO +4 84 days ago $143,800–$230,000
Actively hiring Confirmed live today High trust Competitive pay
SystemVerilog UVM SVA RTL Gate-level Netlist Python Perl Tcl FPGA Emulation Synopsys Cadence Mentor Git DesignSync Mixed-Signal SDF Co-simulation
10+ yrs exp
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SoC Physical Design Verification Engineer

Apple Inc

San Jose, CA 90 days ago $184,700–$324,800
Actively hiring Confirmed live today Low trust Above market
LVS DRC ANT HVDRC Physical Verification Python Perl Tcl Mentor Calibre Synopsys ICV Layout Design Tapeout Design-for-Manufacturing Design-for-Yield Lithography RDL Design
10+ yrs exp
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SoC Design Verification Engineer

Amd

San Jose, CA 90 days ago $141,760–$212,640
Actively hiring Confirmed live today Trusted Below market
System Verilog Verilog UVM C++ C Python Perl SOC Architecture Computer Architecture AXI AHB PCIe DDR Functional Verification Performance Verification Code Coverage Functional Coverage
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Design Verification Engineer

Broadcom

San Jose, CA 130 days ago $143,800–$230,000
Actively hiring Confirmed live today Trusted Competitive pay
System Verilog UVM OVM C++ SystemC Perl RTL Verification ASIC Design Verification FPGA Emulators C Scripting DSP Design Coverage Assertions
10+ yrs exp
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Design Verification Engineer

Broadcom

San Jose, CA 130 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday Trusted Competitive pay
System Verilog UVM OVM C++ SystemC Perl ASIC Design Verification RTL Verification FPGA Emulators Coverage Assertions C Scripting
10+ yrs exp
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SoC Physical Design Verification Engineer

Apple Inc

San Jose, CA 131 days ago $150,400–$277,600
Actively hiring Confirmed live today Low trust Above market
LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Python Perl Tcl Mentor Calibre Synopsys ICV Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD
3+ yrs exp
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SoC Physical Design Verification Engineer

Apple Inc

San Jose, CA 131 days ago $129,300–$194,700
Actively hiring Confirmed live today Low trust Below market
LVS DRC ANT Physical Verification Layout Design RTL to GDS Mentor Calibre Synopsys ICV Design-for-Manufacturing Design-for-Yield Lithography Padring Bump RDL Scripting Signoff Closure
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