below marketmost similar roles pay hereabove market
This role pays less than
53%
of similar roles. Most pay
$168,500–$229,100
— the blue band above.
At the midpoint, this role pays about
$187k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Broadcom
Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software
Broadcom currently has
280 open roles
on FindRole.
Listed pay typically runs
$121,900–$195,000
across 169 roles with salary data.
The Design Verification Engineer joins the ASIC Products Division to lead modeling and verification activities for complex digital and mixed-signal IP blocks. This role involves defining verification plans, designing environment architectures, and developing test bench components, functional models, and test cases. The engineer performs coverage analysis, closure, and debugging of simulation failures at the RTL and gate-level. Key technical requirements include proficiency in SystemVerilog, UVM, and SystemVerilog Assertions to build reusable verification environments. Candidates must utilize Synopsys, Cadence, and Mentor simulation tools alongside scripting languages like Perl, Python, and Tcl. The work focuses on verifying complex circuits such as PLL, DLL, ADC, and DAC components, while potentially utilizing emulation platforms like Palladium, Veloce, and Zebu or Xilinx FPGA prototyping.
What does a Design Verification Engineer earn in California?
Median $199500 from 57 postings across 7 companies.