Senior Staff Design Verification Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $200,000–$300,000 / yr
Posted: 7 days ago
Freshness: Confirmed live yesterday
Closes: Sep 4, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $250k

$133k most similar roles pay here $318k

This role pays more than 90% of similar roles. Most pay $175,000–$223,000 — the shaded band above. At the midpoint, this role pays about $250k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

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At a glance

TL;DR · Senior Staff Design Verification Engineer

Role Posting Log in to save

Sr. Staff Design Verification Engineer joins the Silicon Design Engineering organization to support the development of high-performance computing, AI, and graphics products. This role focuses on front-end design and DFT methodology, where the engineer will drive design-for-test architecture, implementation, and silicon validation across complex SoCs. Key responsibilities include defining test features, driving scan insertion and ATPG generation, executing gate-level simulation strategies, and analyzing test coverage to improve manufacturability. The candidate will utilize Verilog, SystemVerilog, and UVM/OVM methodologies while working with EDA tools like Synopsys DFT Compiler, TestMAX, PrimeTime, and Cadence suites. Technical expertise is required in high-speed interfaces such as HBM, SerDes, and PCIe. Additionally, the role requires proficiency in scripting languages including Python, Perl, Tcl, and Shell to develop scalable automation solutions for large-scale SoC test technologies.

Skills

DFT Verilog SystemVerilog ATPG Scan MBIST LBIST Boundary Scan UVM OVM RTL Design Static Timing Analysis Python Tcl Perl Shell Synopsys DFT Compiler TestMAX PrimeTime VCS Cadence tool s FPGA

What you'll do

Define, implement, and verify DFT architectures and test features for complex SoCs and IP subsystems.
Drive scan insertion, ATPG generation, and test methodology development to meet quality and coverage targets.
Execute gate-level simulation strategies for ATPG pattern validation and test readiness.
Analyze test coverage and diagnose gaps to improve manufacturability and reduce test costs.
Support silicon bring-up, manufacturing test execution, failure analysis, and yield improvement activities.
Develop scalable DFT methodologies, automation solutions, and best practices across various projects.
Provide technical leadership, mentorship, and guidance to engineers across the organization.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Expertise in Design-for-Test (DFT) architecture, implementation, and bring-up for complex semiconductor devices.
Experience implementing DFT solutions for large-scale SoCs including scan, compression, MBIST, LBIST, and boundary scan.
Strong RTL design and integration experience using Verilog and SystemVerilog (preferred).
Experience with high-speed interfaces and complex IPs like HBM, D2D, SerDes, PCIe, and memory subsystems (preferred).
Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and STA (preferred).
Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence suites (preferred).
Strong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages (preferred).

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