Senior Staff Design Verification Engineer

Amd

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $200,000–$300,000 / yr
Posted: 53 days ago
Freshness: Confirmed live today
Closes: Sep 4, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $250k

$132k $318k

below market most similar roles pay here above market

This role pays more than 87% of similar roles. Most pay $177,250–$233,050 — the blue band above. At the midpoint, this role pays about $250k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Senior Staff Design Verification Engineer

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The Sr. Staff Design Verification Engineer joins the FPGA Product and Platform development team to execute technical requirements for Adaptive & Embedded Computing Group device programs from definition to productization. This role involves designing and implementing RTL for complex digital and mixed-signal blocks, supporting physical design activities like synthesis, DFT implementation, and Static Timing Analysis. The engineer will collaborate with Functional Verification teams using SystemVerilog and UVM while utilizing Perl, Tcl, Shell, and Python to maintain design automation flows. Key responsibilities include working with high-speed interfaces such as HBM, SerDes, and PCIe, and utilizing EDA tools like Synopsys DFT Compiler, TestMAX, PrimeTime, and VCS. The position addresses technical challenges in ASIC/SoC development, focusing on silicon implementation and first-time-right software solutions.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

Verilog SystemVerilog UVM DFT RTL Design Python Tcl Perl Shell Static Timing Analysis ASIC SoC FPGA Synopsys Cadence PCIe SerDes HBM Synthesis Place-and-Route

What you'll do

Design and implement RTL for complex digital and mixed-signal blocks using Verilog and SystemVerilog.
Participate in all stages of the design flow from RTL development through GDS implementation.
Support physical design activities including synthesis, DFT implementation, place-and-route, and Static Timing Analysis.
Collaborate with Functional Verification teams to support block-level verification using SystemVerilog and UVM.
Develop and maintain design automation tools and flows using Perl, Tcl, Shell, and Python.
Resolve technical issues and ensure project milestones are achieved with global project teams.
Implement DFT solutions for large-scale SoCs including scan, compression, MBIST, and LBIST.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Design and implement RTL for complex digital and mixed-signal blocks using Verilog and SystemVerilog.
Support physical design activities including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain design automation flows and develop new tools.
Collaborate with Functional Verification teams using constrained-random and directed test environments based on SystemVerilog and UVM.
Strong understanding of the complete ASIC/SoC development flow from RTL architecture through physical implementation and silicon bring-up (preferred).
Experience with high-speed interfaces and complex IPs such as HBM, Die-to-Die, SerDes, PCIe, and memory subsystems (preferred).
Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites (preferred).

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