Digital Design Verification Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CAIrvine, CA
Salary
$101,000–$162,000 / yr
Employment
Full-time
Posted
18 days ago
Freshness
Confirmed live today
Closes
Jan 20, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $132k
$86k most similar roles pay here $245k

This role pays less than 98% of similar roles. Most pay $168,500–$229,100 — the shaded band above. At the midpoint, this role pays about $132k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 172 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 125 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Digital Design Verification Engineer

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The Digital Design Verification Engineer joins the team to manage complex verification tasks for large designs. This role involves taking projects from initial specification through timing closure and physical design hand-off while collaborating cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet milestones. The primary responsibilities include setting up testbenches for Design Verification and performing design debug. To succeed in this position, the candidate must possess high proficiency in UVM and have extensive experience with SoC integration. The work focuses on solving technical challenges within the semiconductor space by ensuring robust verification of integrated circuits. Candidates should be prepared to operate with a high degree of autonomy while utilizing their expertise in UVM test bench setup to ensure project success across various stages of the design lifecycle.

Skills

UVM Design Verification SoC Integration Timing Closure Physical Design Design Debug

What you'll do

  • Set up testbenches for Design Verification using UVM on large designs.
  • Manage the design process from initial specification through timing closure and physical design hand-off.
  • Perform SoC integration tasks as part of the design flow.
  • Execute complex design debug activities to ensure functionality.
  • Mitigate project risks by coordinating with Architecture, Verification, and Physical Design teams.
  • Ensure all project milestones are met on schedule.

What we're looking for

  • BSEE degree required.
  • MSEE or PhD degree (preferred).
  • 5+ years of industry experience in SoC integration, UVM test bench setup, and design debug.
  • Proven track record of setting up testbenches for Design Verification using UVM on large designs.
  • High proficiency in UVM.
  • Ability to take designs from initial specification through timing closure and physical design hand-off.

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