This role pays less than
87%
of similar roles. Most pay
$177,200–$239,462
— the shaded band above.
At the midpoint, this role pays about
$158k
versus about
$208k
for comparable roles.
Based on 240 similar postings.
Employer
About Broadcom
Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software
Broadcom currently has
228 open roles
on FindRole.
Listed pay typically runs
$121,900–$195,000
across 158 roles with salary data.
The Design Verification Engineer joins the ASIC Product Division to support high performance design teams in developing state-of-the-art subsystems for SoC and IP programs. The role involves building verification environments using modern techniques, designing components like UVM agents and behavioral models, and implementing coverage and assertions with System Verilog. Day-to-day tasks include developing random and directed test cases against specifications while analyzing and debugging simulation failures and coverage results. Key technical requirements include proficiency in System Verilog, UVM, OVM, C/C++, Perl, and scripting. The candidate will address complex verification trade-off scenarios for system and sub-block level designs. Relevant domain knowledge includes hardware design, debug, Emulators, FPGA prototyping, and familiarity with CPU, DDR, Bus Protocol, Network Protocol, or DSP designs to ensure products meet specific customer requirements within the semiconductor space.
What does a Design Verification Engineer earn in California?
Median $199724 from 60 postings across 7 companies.