Design Verification Engineer
Broadcom
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Market check
How this pay compares to similar roles
This role pays more than 58% of similar roles. Most pay $159,750–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $188k for comparable roles.
Based on 240 similar postings.
Employer
Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software
Broadcom currently has 119 open roles on FindRole.
Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.
Most-posted roles
At a glance
Design Verification Engineer The Design Verification Engineer joins the ASIC Product Division to support SoC and IP development programs within a high-performance design team. This individual contributor will perform advanced verification tasks, including developing environments using System Verilog and UVM, designing components like UVM agents and behavioral models, and implementing coverage and assertions. The role involves creating random and directed test cases against specifications while analyzing simulation failures and coverage results. Key technical requirements include proficiency in RTL verification methodologies, System Verilog, C/C++, Perl, and scripting. Candidates should possess experience in system and sub-block level verification for hardware designs. Relevant domain knowledge includes CPU, DDR, Bus Protocol, Network Protocol, or DSP design. Additional preferred skills involve working with Emulators, FPGA-based prototyping, and familiarity with overall chip design methodologies to solve complex verification trade-off scenarios.
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