Design Verification Engineer

Broadcom

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
84 days ago
Freshness
Confirmed live yesterday
Closes
Dec 16, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $187k
$125k most similar roles pay here $241k

This role pays more than 58% of similar roles. Most pay $159,750–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

Design Verification Engineer The Design Verification Engineer joins the ASIC Product Division to support SoC and IP development programs within a high-performance design team. This individual contributor will perform advanced verification tasks, including developing environments using System Verilog and UVM, designing components like UVM agents and behavioral models, and implementing coverage and assertions. The role involves creating random and directed test cases against specifications while analyzing simulation failures and coverage results. Key technical requirements include proficiency in RTL verification methodologies, System Verilog, C/C++, Perl, and scripting. Candidates should possess experience in system and sub-block level verification for hardware designs. Relevant domain knowledge includes CPU, DDR, Bus Protocol, Network Protocol, or DSP design. Additional preferred skills involve working with Emulators, FPGA-based prototyping, and familiarity with overall chip design methodologies to solve complex verification trade-off scenarios.

What you'll do

  • Develop verification environments using SystemVerilog and UVM methodologies.
  • Design verification components including UVM agents and behavioral models.
  • Implement coverage and assertions using SystemVerilog.
  • Develop random and directed test cases against technical specifications.
  • Analyze and debug simulation failures at the system and sub-block levels.
  • Analyze coverage results to ensure design requirements are met.
  • Resolve complex verification trade-off scenarios independently.

What we're looking for

  • Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ years of relevant industry experience preferred.
  • Experience verifying designs at both the system level and block level.
  • Fluent knowledge of RTL verification methodologies including SystemVerilog.
  • Strong experience in ASIC design verification flows and DV methodologies.
  • Working knowledge of object-oriented verification languages (OVM, UVM), C/C++, Perl, and scripting skills.
  • Strong independent design debugging capability and ability to resolve complex verification trade-off scenarios.
  • Experience with hardware design, C++/SystemC, Emulators, or FPGA-based prototyping is a plus.
  • Must have legal authorization to work in the US.

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