SoC Physical Design Verification Engineer

What you'll do

• Perform physical verification checks including LVS, DRC, DFM, and lithography at the chip and block levels.
• Drive signoff closure for tapeout by working directly with the implementation team during the design cycle.
• Collaborate with CAD and Technology teams to perform flow bring up and validation.
• Manage project schedules and support cross-functional engineering efforts.
• Design padring, bump, and RDL components in coordination with package and floorplan teams.
• Develop scripts in Perl, Python, or Tcl to debug flow issues and automate verification checks.
• Execute mixed-signal back-end verification checks including ESD and macro placement guidelines.

What we're looking for

• Bachelor of Science degree and 10+ years of relevant industry experience.
• Experience with physical verification flows such as DRC, LVS, ANT, and HVDRC signoff flows (preferred).
• Experience with full-chip integration methodology (preferred).
• Experience with ESD, macro placement design guidelines, and digital/analog mixed signal back-end verification (preferred).
• Knowledge of ASIC physical design and physical verification checks for hierarchical designs (preferred).
• Scripting skills in Perl, Python, or Tcl to debug flow issues and automate checks (preferred).
• Experience with industry standard tools like Mentor Calibre or Synopsys ICV (preferred).
• Tapeout experience with a track record of successful signoffs (preferred); layout design experience is a plus (preferred).