SoC Design Verification Engineer

Amd

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $141,760–$212,640 / yr
Posted: 67 days ago
Freshness: Confirmed live today
Closes: Jul 28, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $177k

$131k most similar roles pay here $243k

This role pays less than 71% of similar roles. Most pay $168,500–$231,300 — the shaded band above. At the midpoint, this role pays about $177k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 512 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 512 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · SoC Design Verification Engineer

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As a SoC Design Verification Engineer, you will join the SOC team to drive and improve the delivery of high-quality technologies. Your daily responsibilities include developing and maintaining tests for functional and performance verification at both the core and SOC levels. You will build testbench components to support next-generation IP, maintain or improve existing test libraries for IP level testing, and be responsible for closing critical verification quality metrics such as pass rates, code coverage, and functional coverage. The role requires proficiency in Verilog, SystemVerilog, UVM, C/C++, and scripting languages like Perl or Python. You will apply your knowledge of SOC architecture, CPU/DSP processors, and industry standard protocols including AXI, AHB, PCIE, and DDR to solve complex problems within the domain of modern processor architecture and digital design.

Skills

System Verilog UVM Verilog C++ C Python Perl SOC Architecture Computer Architecture AXI AHB PCIe DDR Functional Verification Performance Verification Code Coverage Functional Coverage

What you'll do

Develop and maintain tests for functional and performance verification at the core and SOC levels.
Build testbench components to support next-generation IP.
Maintain or improve current test libraries to support IP level testing.
Close verification quality metrics including pass rates, code coverage, and functional coverage.
Provide technical support to other engineering teams.

What we're looking for

Bachelor's or Master's degree in computer engineering or Electrical Engineering.
Strong coding skills in Verilog, SystemVerilog, UVM, C/C++, and scripting languages like Perl or Python (preferred).
Good understanding of SoC architecture, computer architecture, and CPU/DSP processors (preferred).
Understanding of design flow, verification methodology, and computational logic design concepts (preferred).
Experience with industry standard protocols such as AXI, AHB, PCIe, and DDR (preferred).
Strong analytical problem-solving skills and attention to detail.
Excellent written and verbal communication skills.
Ability to collaborate effectively with engineers across different sites and time zones.

10+ yrs exp

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SoC Physical Design Verification Engineer

Apple Inc

San Jose, CA 67 days ago $184,700–$324,800

LVS DRC ANT HVDRC Mentor Calibre Synopsys ICV Python Perl Tcl ASIC Layout Design Tapeout RDL Padring Bump Mixed Signal Physical Verification

10+ yrs exp

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