Design Verification Engineer, Coherent Interconnect

Samsung Electronics

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TXSan Jose, CA
Salary
$151,000–$251,800 / yr
Employment
Full-time
Posted
42 days ago
Freshness
Confirmed live yesterday
Closes
Dec 31, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $201k
$133k most similar roles pay here $265k

This role pays more than 55% of similar roles. Most pay $168,500–$230,087 — the shaded band above. At the midpoint, this role pays about $201k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 84 open roles on FindRole.

Listed pay typically runs $106,000–$200,250 across 78 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Design Verification Engineer, Coherent Interconnect

Design Verification Engineer, Coherent Interconnect will join the System IP & SoC Architecture team to verify system IP including coherent interconnects and caches. The role involves architecting, developing, and maintaining reusable verification environments and testbenches from scratch, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints. You will execute verification strategies, perform code and spec reviews, debug functional failures, and conduct coverage analysis to ensure high-performance, low-latency interconnect solutions for complex SoC designs. Key technical requirements include proficiency in SystemVerilog, UVM, Git version control, and Unix/Perl scripting, along with knowledge of ARM protocols such as CHI, AXI, ACElite, and APB. The work focuses on developing proprietary coherent interconnects and memory controllers to solve performance and power optimization challenges for mobile products, ensuring seamless integration into advanced semiconductor systems and high-performance computing devices.

What does a Design Verification Engineer earn?

Median $195800 from 64 postings across 10 companies.

See salary data

What you'll do

  • Verify System IP including coherent interconnects and caches for high-performance computing devices.
  • Architect, develop, and maintain reusable verification environments and testbenches from scratch using SystemVerilog and UVM.
  • Implement verification strategies and best practices to optimize high-performance, low-latency interconnect solutions.
  • Perform code and specification reviews to ensure feature correctness and design excellence.
  • Debug functional failures from regressions to identify root causes and perform coverage analysis to address gaps.
  • Develop new verification methodologies and improve flows using power-aware verification with UPF and gate-level simulations.
  • Collaborate with cross-functional teams to resolve specification issues and enable successful silicon bring-up.

What we're looking for

  • Bachelor’s degree with 10+ years experience, Master’s with 8+ years, or Ph.D. with 6+ years of experience.
  • 8+ years of professional experience in a design verification role building testbenches from scratch.
  • Strong background in design verification of coherent interconnects (experience with LPDDR memory controllers is preferred).
  • Proficiency in ARM protocols including CHI, AXI, ACElite, and APB.
  • Strong coding skills in SystemVerilog and UVM.
  • Experience with Git version control and Unix/Perl scripting.
  • Formal verification skills (preferred).
  • Authorization to access information subject to U.S. export control laws.

More like this

Similar roles

Staff Design Verification Engineer

Arm Holdings

Austin, TX 163 days ago $198,100–$268,000
SystemVerilog UVM RTL Design AMBA CHI PCIe Compute Express Link Formal Verification Python Perl Cache Coherence Memory Systems Bus Protocols Verification Methodology
8+ yrs exp Hybrid

Staff Design Verification Engineer

Arm Holdings

Austin, TX 17 days ago $198,100–$268,000
SystemVerilog UVM RTL Design AMBA CHI PCIe Compute Express Link Formal Verification Python Perl Cache Coherence Memory Systems Bus Protocols Verification Methodology
8+ yrs exp Hybrid

Integrated Circuit Design Verification Engineer

Snap Inc.

Vancouver, Canada 90 days ago $173,000–$259,000
UVM SystemVerilog Siemens Questa Verilog Python TCL Make Perl Linux ASIC Design Verification RTL Design Emulation MIPI AMBA I2C SPI
10+ yrs exp