Design Verification Engineer
Broadcom
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How this pay compares to similar roles
This role pays more than 58% of similar roles. Most pay $159,750–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $188k for comparable roles.
Based on 240 similar postings.
Employer
Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software
Broadcom currently has 119 open roles on FindRole.
Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.
Most-posted roles
At a glance
The Design Verification Engineer joins the ASIC Product Division to support SoC and IP development programs within a high performance design team. This individual contributor role focuses on state-of-the-art subsystem development to meet specific customer requirements. Daily responsibilities include developing verification environments using modern techniques, designing UVM agents and behavioral models, implementing coverage and assertions with System Verilog, and creating random or directed test cases against specifications. The engineer will also analyze simulation failures and coverage results. Required technical skills include proficiency in System Verilog, UVM, C/C++, Perl, and scripting. Experience with hardware design, debug, Emulators, and FPGA based prototyping is preferred. The role addresses complex verification trade-off scenarios within the domain of SoC and IP development, specifically involving CPU, DDR, Bus Protocol, Network Protocol, or DSP designs.
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