Design Verification Engineer

Broadcom

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Posted
84 days ago
Freshness
Confirmed live yesterday
Closes
Dec 16, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k
This role $187k
$125k most similar roles pay here $241k

This role pays more than 58% of similar roles. Most pay $159,750–$216,250 — the shaded band above. At the midpoint, this role pays about $187k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

The Design Verification Engineer joins the ASIC Product Division to support SoC and IP development programs within a high performance design team. This individual contributor role focuses on state-of-the-art subsystem development to meet specific customer requirements. Daily responsibilities include developing verification environments using modern techniques, designing UVM agents and behavioral models, implementing coverage and assertions with System Verilog, and creating random or directed test cases against specifications. The engineer will also analyze simulation failures and coverage results. Required technical skills include proficiency in System Verilog, UVM, C/C++, Perl, and scripting. Experience with hardware design, debug, Emulators, and FPGA based prototyping is preferred. The role addresses complex verification trade-off scenarios within the domain of SoC and IP development, specifically involving CPU, DDR, Bus Protocol, Network Protocol, or DSP designs.

What you'll do

  • Develop verification environments using SystemVerilog and UVM methodologies.
  • Design verification components including UVM agents and behavioral models.
  • Implement coverage metrics and assertions using SystemVerilog.
  • Develop random and directed test cases against technical specifications.
  • Analyze and debug simulation failures at the system and sub-block levels.
  • Analyze coverage results to ensure design requirements are met.
  • Resolve complex verification trade-off scenarios during the development process.

What we're looking for

  • Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ years of relevant industry experience.
  • Legal authorization to work in the United States.
  • Experience verifying designs at both system and block levels.
  • Fluent knowledge of RTL verification methodologies including SystemVerilog.
  • Strong experience in ASIC design verification flows and DV methodologies.
  • Working knowledge of object-oriented verification languages (OVM, UVM), C/C++, Perl, and scripting skills.
  • Strong independent design debugging capabilities and ability to resolve complex verification trade-off scenarios.
  • Proficiency in developing verification environments, components, coverage, assertions, and test cases.

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