Design Verification Engineer

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
130 days ago
Freshness
Confirmed live today
Closes
Dec 16, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $187k
$133k $240k
below market most similar roles pay here above market

This role pays less than 53% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $187k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the ASIC Product Division within a high performance design team focused on state-of-the-art subsystem development. This role involves performing advanced verification tasks for SoC and IP development programs to meet specific customer requirements. Key responsibilities include developing verification environments using modern techniques, designing UVM agents and behavioral models, and implementing coverage and assertions using System Verilog. The engineer will develop random and directed test cases, analyze simulation failures, and evaluate coverage results. Required technical skills include fluency in RTL verification methodologies, System Verilog, C/C++, Perl, and scripting. The role requires expertise in hardware design and debug, with preferred knowledge of CPU, DDR, Bus, Network, or DSP protocols, as well as experience with Emulators and FPGA based prototyping.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

System Verilog UVM OVM C++ SystemC Perl RTL Verification ASIC Design Verification FPGA Emulators C Scripting DSP Design Coverage Assertions

What you'll do

  • Develop verification environments using System Verilog and UVM.
  • Design verification components including UVM agents and behavioral models.
  • Implement coverage and assertions using System Verilog.
  • Develop random and directed test cases against specifications.
  • Analyze and debug simulation failures.
  • Analyze coverage results to ensure design verification goals are met.
  • Resolve complex verification trade-off scenarios.

What we're looking for

  • Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ years of relevant industry work experience.
  • Experience in verifying designs at the system level and block level.
  • Fluent knowledge of RTL verification methodologies including System Verilog.
  • Strong experience in ASIC design verification flows and DV methodologies.
  • Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.
  • Strong and independent design debugging capability.
  • Must have legal authorization to work in the US.
  • Experience with hardware design, C++/SystemC, Emulators, FPGA prototyping, or knowledge of CPU/DDR/Bus/Network/DSP design (preferred).

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