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Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools +11 more Show less

Physical Design Synthesis Floorplanning Placement Routing Timing Closure STA DRC LVS Python TCL Shell Perl Synopsys Cadence ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC Calibre ICV +18 more Show less

Physical Design GPU SoC Synthesis Floorplanning Placement Routing Clock Tree Synthesis Timing Closure STA Signoff DRC LVS Python Tcl Shell Perl Synopsys Cadence ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC +20 more Show less

ASIC RTL-to-GDSII Floorplanning Place and Route Static Timing Analysis PrimeTime TCL Python Cadence Innovus Cadence Genus Synopsys Formality Mentor Calibre Apache Redhawk Voltus Physical Verification +10 more Show less

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting EDA Tools VLSI CMOS ECO Tapeout Digital Logic Design +12 more Show less

Physical Design RTL Synthesis DFT Floorplanning Place and Route STA VLSI TCL Python Perl Shell Scripting EDA Tools PPA Power Distribution CMOS Tapeout +12 more Show less

Physical Design ASIC RTL PPA Optimization Floorplanning Place and Route DFT Synthesis TCL Python Perl Multi-voltage Tapeout Design for Yield Thermal Management +10 more Show less

ASIC Physical Design Clock Distribution Floorplanning P&R Timing Verification Netlist to Tapeout SoC Power Distribution Signal Planning ESD multi Vt Design for Yield Manufacturability GPU Architecture +10 more Show less

Physical Design DDR Floor Planning Clock Tree Synthesis Place and Route PDN Timing Analysis LVS DRC SoC Micro-architecture +6 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Physical Design +11 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture +11 more Show less

ASIC Physical Design Floorplanning Power Planning Clock Tree Synthesis Static Timing Analysis Signal Integrity RC Extraction DFT UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime +14 more Show less

Physical Design Synthesis PnR STA CTS Floorplanning Routing UPF Python Tcl Innovus ICC2 Fusion Compiler Genus PrimeTime Tempus LEC VLSI +13 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation SoC IC Package +6 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction Timing Closure CTS POCV AOCV +12 more Show less

Physical Design SPICE RTL Standard Cell Optimization PLL Circuit Design Verification Jitter Measurement Hardware Engineering +4 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC +5 more Show less

ASIC Physical Design Synthesis P&R Timing Analysis Fusion Compiler Synopsys FC ICC2 Cadence Genus Innovus Scripting Logic Optimization Clock Tree Synthesis Power Optimization Physical Design Convergence +9 more Show less

Physical Design Cadence Innovus Tcl Python Place-and-Route Timing Analysis Physical Verification Digital Design Automation Micro-architecture Logic Design +6 more Show less